tag: deep learning

Energy-efficient memcapacitor devices for neuromorphic computing
By Technical Paper Link - 03 Nov, 2021 - Comments: 0

Abstract Data-intensive computing operations, such as training neural networks, are essential for applications in artificial intelligence but are energy intensive. One solution is to develop specialized hardware onto which neural networks can be directly mapped, and arrays of memristive devices can, for example, be trained to enable parallel multiply–accumulate operations. Here we show that ... » read more

Fabs Drive Deeper Into Machine Learning
By Anne Meixner - 07 Sep, 2021 - Comments: 0

Advanced machine learning is beginning to make inroads into yield enhancement methodology as fabs and equipment makers seek to identify defectivity patterns in wafer images with greater accuracy and speed. Each month a wafer fabrication factory produces tens of millions of wafer-level images from inspection, metrology, and test. Engineers must analyze that data to improve yield and to reject... » read more

NN-Baton: DNN Workload Orchestration & Chiplet Granularity Exploration for Multichip Accelerators
By Technical Paper Link - 14 Jun, 2021 - Comments: 0

"Abstract—The revolution of machine learning poses an unprecedented demand for computation resources, urging more transistors on a single monolithic chip, which is not sustainable in the Post-Moore era. The multichip integration with small functional dies, called chiplets, can reduce the manufacturing cost, improve the fabrication yield, and achieve die-level reuse for different system scales... » read more

Applications, Challenges For Using AI In Fabs
By Mark LaPedus - 14 Apr, 2021 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss chip scaling, transistors, new architectures, and packaging with Jerry Chen, head of global business development for manufacturing & industrials at Nvidia; David Fried, vice president of computational products at Lam Research; Mark Shirey, vice president of marketing and applications at KLA; and Aki Fujimura, CEO of D2S. Wh... » read more

A Novel Complementary Architecture of One-time-programmable Memory and Its Applications as Physical Unclonable Function (PUF) and One-time Password
By Technical Paper Link - 31 Mar, 2021 - Comments: 0

Abstract "For the first time, we proposed a 2T complementary architecture of one-time-programmable memory (OTP) in a foundry logic CMOS chip. It was then used to realize the PUF (Physical unclonable function), and the combination with the AI technology to provide a one-time password capability. At first, an OTP was developed based on a novel 2T CMOS unit cell. The experimental results show t... » read more

Deep Learning (DL) Applications In Photomask To Wafer Semiconductor Manufacturing
By eBeam Initiative - 17 Mar, 2021 - Comments: 0

The Survey: 2021 Deep Learning Applications List by eBeam Initiative members is a list of current deep learning efforts that are being used in photomask to wafer semiconductor manufacturing. Examples come from ASML, D2S, Fraunhofer IPMS, Hitachi High-Tech Corporation, imec, Siemens Industries Software, Inc., Siemens EDA, STMicroelectronics, and TASMIT. Published by the eBeam Initiative Membe... » read more

Single Chip Auto-Valet Parking System with TDA4VMID SoC
By Technical Paper Link - 15 Feb, 2021 - Comments: 0

Abstract "Auto-Valet parking is a key emerging function for Advanced Driver Assistance Systems (ADAS) enhancing traditional surround view system providing more autonomy during parking scenario. Auto-Valet parking system is typically built using multiple HW components e.g. ISP, micro-controllers, FPGAs, GPU, Ethernet/PCIe switch etc. Texas Instrument’s new Jacinto7 platform is one of industry... » read more

Hidden Costs In Faster, Low-Power AI Systems
By Ed Sperling - 20 Jan, 2021 - Comments: 1

Chipmakers are building orders of magnitude better performance and energy efficiency into smart devices, but to achieve those goals they also are making tradeoffs that will have far-reaching, long-lasting, and in some cases unknown impacts. Much of this activity is a direct result of pushing intelligence out to the edge, where it is needed to process, sort, and manage massive increases in da... » read more

PowerPlanningDL: Reliability-Aware Framework for On-Chip Power Grid Design using Deep Learning
By Technical Paper Link - 31 Dec, 2020 - Comments: 0

Academic research paper from Dept. of CSE, IIT Guwahatim, India. Abstract: "With the increase in the complexity of chip designs, VLSI physical design has become a time-consuming task, which is an iterative design process. Power planning is that part of the floorplanning in VLSI physical design where power grid networks are designed in order to provide adequate power to all the underlying ... » read more

AI And High-NA EUV At 3/2/1nm
By Mark LaPedus - 16 Dec, 2020 - Comments: 1

Semiconductor Engineering sat down to discuss lithography and photomask issues with Bryan Kasprowicz, director of technology and strategy and a distinguished member of the technical staff at Photronics; Harry Levinson, principal at HJL Lithography; Noriaki Nakayamada, senior technologist at NuFlare; and Aki Fujimura, chief executive of D2S. What follows are excerpts of that conversation. To vie... » read more

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