tag: degradation models

Degradation Monitoring
By proteanTecs - 09 Mar, 2020 - Comments: 0

This paper describes a reliability degradation modeling and monitoring method based on a combination of IC novel embedded circuits (Agents), and off-chip machine learning algorithms which infer the digital readouts of these circuits during test and operational lifetime. Together, they monitor the margin degradation of an IC, as well as other vital parameters of the IC and its environmental s... » read more

Toward Consistent Circuit-Level Aging Simulations In Different EDA Environments
By Fraunhofer IIS/EAS - 10 Apr, 2019 - Comments: 0

Aging simulations on circuit level allow integrated circuit (IC) designers to verify their circuits with respect to lifetime reliability requirements by considering the degradation of field effect transistors (FETs). To obtain significant analysis results with a reasonable effort, two prerequisites have to be fulfilled. First, reasonable models for FET degradation effects have to be set up. Sec... » read more

Chip Aging Accelerates
By Ed Sperling - 14 Feb, 2018 - Comments: 1

Reliability is becoming an increasingly important proof point for new chips as they are rolled out in new markets such as automotive, cloud computing and industrial IoT, but actually proving that a chip will function as expected over time is becoming much more difficult. In the past, reliability generally was considered a foundry issue. Chips developed for computers and phones were designed ... » read more

Circuit-Level Aging Simulations Predict The Long-Term Behavior Of ICs
By Fraunhofer IIS/EAS - 10 Jan, 2018 - Comments: 0

Reliability is a major criterion for integrated circuits (ICs) in safety critical applications, such as automotive, medical, or aviation electronics. A particular effect that contributes to wear-out is device (i.e. transistor) degradation. Its impact on the circuit behavior can be verified by circuit level aging simulations, which are offered by various EDA vendors. However, reasonable results ... » read more

Tech Talk: Substrate Noise Coupling
By Ed Sperling - 14 Dec, 2017 - Comments: 0

Roland Jancke, head of the department for design methodology for the Fraunhofer's Engineering of Adaptive Systems Division, talks with Semiconductor Engineering about the impact of substrate noise coupling on reliability of chips and how to deal with this issue. https://youtu.be/7E2rCwYr6-o » read more

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