tag: delamination

Speeding Up Acoustic Wafer Inspection
By Ed Sperling - 09 Dec, 2024 - Comments: 0

Higher density and more vertical layers require higher-resolution inspection. In the past that generally resulted in longer scan times, which can slow throughput in the fab or assembly house. Bryan Schackmuth, senior product line manager at Nordson Test & Inspection, explains how rotational scanning using acoustic wafer inspection can speed up inspection time by a factor of eight, why it is... » read more

SiC Growth For EVs Is Stressing Manufacturing
By Anne Meixner - 08 Aug, 2023 - Comments: 0

The electrification of vehicles is fueling demand for silicon carbide power ICs, but it also is creating challenges in finding and identifying defects in those chips. Coinciding with this is a growing awareness about just how immature SiC technology is and how much work still needs to be done — and how quickly that has to happen. Automakers are pushing heavily into electric vehicles, and t... » read more

Will An Adhesion Promoter Prevent Delamination In Power Semiconductor Packages?
By Amkor - 21 Jul, 2021 - Comments: 0

Power semiconductor packages are used in high temperature, high voltage environments. With the increase of electric vehicles (EVs) and hybrid electric vehicles (HEV) in the automotive market, demands on (and for) power packages have been growing. Packages for automotive applications must pass extensive testing for safety, therefore, packaging reliability is essential. As more semiconductor pack... » read more

Failure Analysis Of Electronic Devices Using Scanning Acoustic Microscopy
By Yavuz Kose - 11 Jun, 2019 - Comments: 0

Scanning acoustic microscopy, or SAM, is a non-destructive technique used in failure analysis of complex devices. SAM can provide a resolution down to sub-micron thicknesses. SAM is an efficient tool for analysis of adhesion between layers and presence of possible flaws in each layer. This can be used e.g. for investigations of sealing, coating, flip-chip underfills, BGA, QFN, wafer to wafer ... » read more

Challenges And Solutions For Silicon Wafer Bevel Defects During 3D NAND Flash Manufacturing
By Pradeep Nanja - 23 May, 2019 - Comments: 0

As semiconductor technology scales down in size, process integration complexity and defects are increasing in 3D NAND flash, partially due to larger stack deposits and thickness variability between the wafer center and the wafer edge. Industry participants are working to reduce defect density at the wafer edge to improve overall wafer yield. Attention has focused on common wafer bevel defects s... » read more

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