EDA Software Design Flow Considerations For The RF/Microwave Module Designer

By Cadence - 25 May, 2022 - Comments: 0

Miniaturization of consumer products, aerospace and defense systems, medical devices, and LED arrays has spawned the development of a technology known as the multi-chip module (MCM), which combines multiple integrated circuits (ICs), semiconductor die, and other discrete components within a unifying substrate for use as a single component. This white paper outlines the steps for implementing an... » read more

Preparing For Test Early In The Design Flow

By Ann Mutschler - 02 Mar, 2022 - Comments: 0

Until very recently, semiconductor design, verification, and test were separate domains. Those domains have since begun to merge, driven by rising demand for reliability, shorter market windows, and increasingly complex chip architectures. In the past, products were designed from a functional perspective, and designers were not concerned about what the physical implementation of the product ... » read more

RF/Microwave EDA Software Design Flow Considerations For PA MMIC Design

By Cadence - 09 Feb, 2022 - Comments: 0

In this white paper, a gallium arsenide (GaAs) pseudomorphic high-electron mobility transistor (pHEMT) power amplifier (PA) design approach is examined from a systems perspective. It highlights the design flow and its essential features for most PA design projects by illustrating a simple Class A GaAs pHEMT monolithic microwave IC (MMIC) PA design using Cadence AWR Microwave Office circuit desi... » read more

A New Vision For Memory Chip Design And Verification

By Anand Thiruvengadam - 02 Sep, 2021 - Comments: 0

Discrete memory chips are arguably the most visible reminder of the opportunities and challenges for advanced semiconductor design. They are manufactured in huge quantities, becoming key drivers for new technology nodes and new fabrication processes. Price fluctuations have a major impact on the financial health of the electronics industry, and any shortages can shut down the manufacturing line... » read more

Solution Efficiencies For Dynamic Function eXchange Using Abstract Shells

By Xilinx - 04 Aug, 2021 - Comments: 0

Dynamic Function eXchange (DFX) enables great flexibility within Xilinx® silicon, empowering you to load applications on demand, deliver updates to deployed systems, and reduce power consumption. Platform designs allow for collaboration between groups, where one group can focus on infrastructure and another on hardware acceleration. However, DFX has fundamental flow requirements that lead to l... » read more

Optimize Physical Verification Cost Of Ownership With Elastic CPU Management

By Synopsys - 07 Jul, 2021 - Comments: 0

For physical verification, advanced process technology nodes create implementation challenges. Design sizes have gotten larger and required rules from foundries have become more numerous in count (thousands) and more complex (hundreds of discrete steps). For these reasons, physical verification tools have been able to span these jobs not only across multiple CPUs on a single physical compute ho... » read more

Silo Busting In The Design Flow

By Brian Bailey - 24 Nov, 2020 - Comments: 0

An increasing number of dependencies in system design are forcing companies, people, tools, and flows to become more collaborative. Design and EDA companies must adapt to this new reality because it has become impossible for anyone to do it all by themselves. Moreover, what happens in manufacturing and packaging needs to be considered up front, and what gets designed in the design phase may ... » read more

Gaps Emerging In System Integration

By Brian Bailey - 29 Jun, 2020 - Comments: 0

The system integration challenge is evolving, but existing tools and methods are not keeping up with the task. New tools and flows are needed to handle global concepts, such as power and thermal, that cannot be dealt with at the block level. As we potentially move into a new era where IP gets delivered as physical pieces of silicon, this lack of an accepted flow will become a stumbling block. ... » read more

Over-Design, Under-Design Impacts Verification

By Ann Mutschler - 25 Jun, 2020 - Comments: 0

Designing a complex chip today and getting it out the door on schedule and within budget — while including all of the necessary and anticipated features and standards — is forcing engineering teams to make more tradeoffs than in the past, and those tradeoffs now are occurring throughout the flow. In an ideal system design flow, design teams will have done early, pre-design analysis to se... » read more

Fusion Technology

By Synopsys - 22 Apr, 2020 - Comments: 0

Learn how the recent semiconductor industry shifts are breaking the traditional RTL-to-GDSII flow, and how the new Synopsys Fusion Technology helps you cross the chasm. To read more, click here. » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?