tag: device scaling

Scaling Sideways
By Ed Sperling - 19 Jul, 2018 - Comments: 0

The next steps in semiconductor technology don't follow the same vectors. While 3nm chips are likely to roll out at some point in the future, it's not clear what the business case will be for developing them. What's clear is the number of companies developing chips at that node will shrink to a handful (or less), because they're going to be far too expensive to design, verify and manufacture... » read more

New Transistor Types Vs. Packaging
By Ed Sperling - 11 Jun, 2018 - Comments: 0

Plans are being formulated for the rollout of multiple types of gate-all-around FETs and literally dozens of advanced packaging options. The question now is which ones will achieve critical mass, because there aren't enough chips in the world to support all of them profitably. FinFETs, which were first introduced by Intel at 22nm, are running out of steam. While they will survive 10/7nm, and... » read more

The Power Of De-Integration
By Ed Sperling - 17 May, 2018 - Comments: 0

The idea that more functionality can be added into a single chip, or even into a single system, is falling out of vogue. For an increasing number of applications, it's no longer considered the best option for boosting performance or lowering power, and it costs too much. Hooman Moshar, vice president of engineering at Broadcom, said in a keynote speech at Mentor's User2User conference this w... » read more

More Lithography/Mask Challenges (Part 3)
By Mark LaPedus - 16 May, 2018 - Comments: 1

Semiconductor Engineering sat down to discuss lithography and photomask technologies with Gregory McIntyre, director of the Advanced Patterning Department at [getentity id="22217" e_name="Imec"]; Harry Levinson, senior fellow and senior director of technology research at [getentity id="22819" comment="GlobalFoundries"]; Regina Freed, managing director of patterning technology at [getentity id="... » read more

More Nodes, New Problems
By Ann Mutschler - 26 Apr, 2018 - Comments: 0

The rollout of leading-edge process nodes is accelerating rather than slowing down, defying predictions that device scaling would begin to subside due to rising costs and the increased difficulty of developing chips at those nodes. Costs are indeed rising. So are the number of design rules, which reflect skyrocketing complexity stemming from multiple patterning, more devices on a chip, and m... » read more

New Patterning Options Emerging
By Mark LaPedus - 19 Apr, 2018 - Comments: 1

Several fab tool vendors are rolling out the next wave of self-aligned patterning technologies amid the shift toward new devices at 10/7nm and beyond. Applied Materials, Lam Research and TEL are developing self-aligned technologies based on a variety of new approaches. The latest approach involves self-aligned patterning techniques with multi-color material schemes, which are designed for us... » read more

Nodes Vs. Nodelets
By Mark LaPedus - 22 Jan, 2018 - Comments: 0

Foundries are flooding the market with new nodes and different process options at existing nodes, spreading confusion and creating a variety of challenges for chipmakers. There are full-node processes, such as 10nm and 7nm, with 5nm and 3nm in R&D. But there also is an increasing number of half-nodes or "node-lets" being introduced, including 12nm, 11nm, 8nm, 6nm and 4nm. Node-lets ar... » read more

The Next 5 Years Of Chip Technology
By Ed Sperling - 15 Jan, 2018 - Comments: 1

Semiconductor Engineering sat down to discuss the future of scaling, the impact of variation, and the introduction of new materials and technologies, with Rick Gottscho, CTO of [getentity id="22820" comment="Lam Research"]; Mark Dougherty, vice president of advanced module engineering at [getentity id="22819" comment="GlobalFoundries"]; David Shortt, technical fellow at [getentity id="22876" co... » read more

Fan-Outs vs. TSVs
By Jeff Dorsch - 13 Dec, 2017 - Comments: 0

Two years ago, at the annual IMAPS conference on 2.5D and 3D chip packaging, the presentations were dominated by talk of fan-out wafer-level packaging. There was almost no talk of through-silicon vias, which previously had been heralded as vital to 2.5D and 3DIC packaging. Fast forward to this month's 3D Architectures for Heterogeneous Integration and Packaging conference in Burlingame, Cali... » read more

What’s After 7nm?
By Ed Sperling - 14 Sep, 2017 - Comments: 1

The rollout of 10/7nm was a long time coming, and for good reason. It's hard stuff, and chipmakers have to be ready to take a giant step forward with new processes, tools, and to deal with a slew of physical effects that no longer can be handled by just guard-banding a design. The big question is what's next, when it will happen, and how much it will cost. Preparing for the next process node... » read more

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