The Power Of De-Integration

Pushing the laws of physics is becoming far too expensive for most chipmakers.


The idea that more functionality can be added into a single chip, or even into a single system, is falling out of vogue. For an increasing number of applications, it’s no longer considered the best option for boosting performance or lowering power, and it costs too much.

Hooman Moshar, vice president of engineering at Broadcom, said in a keynote speech at Mentor’s User2User conference this week that power is driving “de-integration.”

“Integration has always been an effective way to increase function and lower cost,” Moshar said. “But porting IPs to smaller nodes is risky. It costs money and time, which can lead to market delays. Power and cost materially influence process node migration.”

Shrinking lines and spaces comes with an increasing power penalty at each new node, requiring complex management schemes so that chips don’t burn up. Power also is linked to a number of other issues, such as noise, electromigration, and premature circuit aging.

While these effects can be controlled, remediation requires a significant amount of engineering work. For each new node after 10/7nm, the cost per nanometer can be measured in tens to hundreds of millions of dollars in design costs, and billions of dollars in manufacturing equipment costs. And even then, performance improvements are not as large as at past nodes.

If Moshar’s prognosis is correct—and there appears to be a rising tide of evidence to support this—then semiconductor design and manufacturing are beginning to splinter. While a handful of companies will continue driving forward to the latest process node, an increasing number are taking a different path. This already is evident at 22nm, where foundries are positioning for a major battle. This is the last node where planar transistors can be used, and GlobalFoundries, TSMC and Intel are preparing to slug it out. GlobalFoundries has been winning business with its FD-SOI technology, and TSMC and Intel have tweaked bulk CMOS to minimize power. Intel’s 22nm option uses its finFET technology to control leakage.

The activity at 22nm is both a reflection of new markets that are opening up for semiconductors, as well as a recognition that systems are becoming broader than individual devices. The push to 5G, an explosion of activity in the cloud, and even cryptocurrency mining and blockchains all point to the rapid movement of data and a more distributed processing approach. So rather than thinking of a device as a system, the system is really a collection of devices that may or may not be owned by a single person or entity.

This may sound like a minor change, but it can have profound repercussions throughout the semiconductor supply chain. “De-integration” is another way of saying that only digital logic benefits from scaling, and even there architectural design can compensate for some of the performance improvements.

This raises some questions about the continued pace of node migration, the future of nodelets, and the fundamental business equation behind device scaling. And it potentially opens the door to disaggregation in the semiconductor business, which has been on a consolidation tear over the past few years. De-integration of chips and redefining of systems could lead to de-integration of the industry that supports them, and that’s something everyone should be watching.

Leave a Reply