tag: DFT

The Great Test Blur
By Ed Sperling - 06 Aug, 2019 - Comments: 0

As chip design and manufacturing shift left and right, concerns over reliability are suddenly front and center. But figuring out what exactly what causes a chip to malfunction, or at least not meet specs for performance and power, is getting much more difficult. There are several converging trends here, each of which plays an integral role in improving reliability. But how significant a role... » read more

Hierarchical DFT On A Flat Layout Design
By Vidya Neerkundar - 06 Aug, 2019 - Comments: 0

The use of hierarchical DFT methods is growing as design size and complexity stresses memory requirements and design schedules.  Hierarchical DFT divides the design into smaller pieces, creates test structures and patterns at the core level, then retargets the core patterns to the chip level. But, if you need to perform the physical place and route on the full flat design, can you still take a... » read more

ON Semiconductor Reduces Memory BiST Insertion Time By 6X With Tessent Hierarchical Flow
By Mentor, a Siemens Business - 05 Aug, 2019 - Comments: 0

This paper describes a case study on the insertion of memory BiST for an ON Semiconductor multi-million gate-level netlist with 300 memory instances. The physical implementation will be done using a flat layout. Two different methodologies can be applied when it comes to physical implementation; hierarchical or fullflat. When performing physical implementation as full-flat flow, typically the D... » read more

Meeting ISO 26262 Requirements Using Tessent IC Test Solutions
By Mentor, a Siemens Business - 08 Jul, 2019 - Comments: 0

As the industry moves towards greater automation in vehicles, suppliers of the ICs used to drive the automotive electronic systems are rapidly adopting solutions to meet ISO 26262 requirements. The Tessent family of IC test products offers the highest defect coverage, in-system non-destructive memory test, hybrid ATPG/Logic BIST, and analog test coverage measurement. These technologies add up t... » read more

BiST Grows Up In Automotive
By Ann Mutschler - 12 Jun, 2019 - Comments: 0

Test concepts and methods that have been used for many years in traditional semiconductor and SoC design are now being leveraged for automotive chips, but they need to be adapted and upgraded to enable monitoring of advanced automotive systems during operation of a vehicle. Automotive and safety critical designs have very high quality, reliability, and safety requirements, which pairs pe... » read more

Smart Plug-And-Play DFT For Arm Cores
By Ron Press - 11 Jun, 2019 - Comments: 0

Modern SoCs are experiencing continued growth in capabilities and design sizes with more and more subsystem IPs being implemented. These large, complex, multi-core SoCs need strategies for DFT and ATPG that effectively reduce DFT effort, minimize ATPG runtime, and still achieve the target test coverage. Hierarchical DFT enables designing and testing of these designs in a systematic and repeatab... » read more

ATE Lab To Fab
By Ed Sperling - 05 Jun, 2019 - Comments: 2

Shu Li, business development manager at Advantest, zeroes in on the communication gap between engineers on the design side and the manufacturing/test side, why it exists, and what needs to be done to bridge that gap in order to speed up and improve test quality. https://youtu.be/Nd-5_twbJBw     See other tech talk videos here » read more

Making AI More Dependable
By Ed Sperling - 07 May, 2019 - Comments: 0

Ira Leventhal, vice president of Advantest’s new concept product initiative, looks at why AI has taken so long to get going, what role it will play in improving the reliability of all chips, and how to use AI to improve the reliability of AI chips themselves. » read more

Automotive, AI Drive Big Changes In Test
By Ann Mutschler - 25 Apr, 2019 - Comments: 0

Design for test is becoming enormously more challenging at advanced nodes and in increasingly heterogeneous designs, where there may be dozens of different processing elements and memories. Historically, test was considered a necessary but rather mundane task. Much has changed over the past year or so. As systemic complexity rises, and as the role of ICs in safety-critical markets continues ... » read more

The Precision Knob
By Ed Sperling - 18 Apr, 2019 - Comments: 0

Precision used to be a goal, but increasingly it is being used as a tool. This is true for processing and algorithms, where less precision can greatly improve both performance and battery life. And it is true in manufacturing, where more precision can help minimize the growing impact of variation. Moreover, being able to dial precision up or down can help engineers see the impact on a system... » read more

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