tag: DFT

Testing The Stack: DFT Is Ready For 3D Devices
By Martin Keim - 08 Sep, 2022 - Comments: 0

When existing advanced 2D designs already push the limits of design-for-test (DFT) tools, what hope do developers have of managing DFT for 3D devices? Can anyone afford the tool run time, on-chip area demand, pattern count, and test time? The answer, from an array of experts, is yes, there is a path to a scalable, affordable, and comprehensive DFT solution for 3D ICs. Well-covered strategies... » read more

Affordable And Comprehensive Testing Of 3D Stacked Die Devices
By Siemens EDA - 07 Sep, 2022 - Comments: 0

Developers of high-end semiconductor products who face manufacturing limitations with respect to die sizes are investing in 3D stacked die technology. These advanced designs already push current design-for-test (DFT) solutions to the limits: tool run time, on-chip area demand, test pattern count, and test time. How then, can designers manage DFT for these new 3D devices? In this paper, we outli... » read more

Semiconductor Test: Staying Ahead Of Nanodevices
By Tucker Davis - 07 Jun, 2022 - Comments: 0

In the semiconductor fabrication process, engineers continue to innovate, enabling smaller transistors and higher density circuits. The transition to finFETs allowed 7nm and 5nm processes to realize circuits of amazing density, and the progress of nanosheet transistors provides confidence in the future advancement of digital circuit cost reduction and performance improvement. As individual t... » read more

Automation Of Shared Bus Memory Test With Tessent MemoryBIST
By Siemens EDA - 12 Apr, 2022 - Comments: 0

New requirements in automotive, artificial intelligence (AI), and processor applications have resulted in increased use of memory-heavy IP. Memory-heavy IPs for these applications are optimized for high performance, and they will often have a single access point for testing the memories. Tessent MemoryBIST provides an out-of-the-box solution for using this single access point, or shared bus int... » read more

Automate Memory Test Through A Shared Bus Interface
By Harshitha Kodali - 12 Apr, 2022 - Comments: 0

The use of memory-heavy IP in SoCs for automotive, artificial intelligence (AI), and processor applications is steadily increasing. However, these memory-heavy IP often have only a single access point for testing the memories. A shared bus architecture allows testing and repairing memories within IP cores through a single access point referred to as a shared bus interface. Within this interface... » read more

Software-Driven and System-Level Tests Drive Chip Quality
By Bryon Moyer - 08 Mar, 2022 - Comments: 0

Traditional semiconductor testing typically involves tests executed by automatic test equipment (ATE). But engineers are beginning to favor an additional late-test pass that tests systems-on-chip (SoCs) in a system context in order to catch design issues prior to end-product assembly. “System-level test (SLT) gives a high-volume environment where you can test the hardware and software toge... » read more

A Practical Approach To DFT For Large SoCs And AI Architectures, Part II
By Rahul Singhal - 08 Mar, 2022 - Comments: 0

By Rahul Singhal and Giri Podichetty Part I of this article discusses the design-for-test (DFT) challenges of AI designs and strategies to address them at the die level. This part focuses on the test requirements of AI chips that integrate multiple dies and memories on the same package. Why 2.5D/3D chiplet-based designs for AI SoCs? Many semiconductor companies are adopting chiplet-based d... » read more

Preparing For Test Early In The Design Flow
By Ann Mutschler - 02 Mar, 2022 - Comments: 0

Until very recently, semiconductor design, verification, and test were separate domains. Those domains have since begun to merge, driven by rising demand for reliability, shorter market windows, and increasingly complex chip architectures. In the past, products were designed from a functional perspective, and designers were not concerned about what the physical implementation of the product ... » read more

Smart DFT Infrastructure And Automation Are Key To Managing Design Scaling
By Siemens EDA - 08 Feb, 2022 - Comments: 0

This paper describes how using a smarter DFT infrastructure and automation can greatly improve the DFT schedule. A structural DFT infrastructure based on plug-and-play principles is used to enable concurrent DFT development and integration. DFT automation is used to connect and manage the DFT infrastructure to dramatically reduce the risks associated with design scaling and complexity. Highe... » read more

Simplify DFT For Advanced SoCs
By Ron Press - 08 Feb, 2022 - Comments: 0

The purpose of electronic design automation (EDA) software is to solve SoC design problems and simplify the entire process. For design for test (DFT), this means aiming to streamline the DFT development for today’s large and complex designs. The technologies and methods developed through partnerships between EDA suppliers, foundries, and semiconductor companies should effectively reduce risk,... » read more

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