What’s Changing In DRAM


Most of the attention in chip scaling has been focused on logic and on-chip memory, but off-chip memory is starting to encounter problems, as well. David Fried, vice president of computational products at Lam Research, looks at the impact of shrinking features and increasing density, including variation, thermal effects and aging, as well as effects such as micro-loading and DRAM stacking. » read more

Will Monolithic 3D DRAM Happen?


As DRAM scaling slows, the industry will need to look for other ways to keep pushing for more and cheaper bits of memory. The most common way of escaping the limits of planar scaling is to add the third dimension to the architecture. There are two ways to accomplish that. One is in a package, which is already happening. The second is to sale the die into the Z axis, which which has been a to... » read more

SMASH: Synchronized Many-sided Rowhammer Attacks from JavaScript


Authors: Finn de Ridder, ETH Zurich and VU Amsterdam; Pietro Frigo, Emanuele Vannacci, Herbert Bos, and Cristiano Giuffrida, VU Amsterdam; Kaveh Razavi, ETH Zurich Abstract: "Despite their in-DRAM Target Row Refresh (TRR) mitigations, some of the most recent DDR4 modules are still vulnerable to many-sided Rowhammer bit flips. While these bit flips are exploitable from native code, tri... » read more

Memory Technology: Innovations needed for continued technology scaling and enabling advanced computing systems


Abstract: "An increasing demand for data generation, storage, and intelligence generation from data is driving advances in memory technology and advanced computing applications. Memory performance is starting to define modern day computing in both mobile and server environments. There is an absolute need to continue the tremendous pace of memory technology improvements to deliver performanc... » read more

Dynamic Flash Memory with Dual Gate Surrounding Gate Transistor (SGT)


Abstract: "This paper proposes an ultra-scaled memory device, called `Dynamic Flash Memory (DFM)'. With a dual-gate Surrounding Gate Transistor (SGT), a capacitorless 4F2 cell can be achieved. Similar to DRAM [1], refresh is needed, but high speed block refresh can improve the duty ratio. Analogous to Flash [2], three fundamental operations of “0” Erase, “1” Program, and Read are nee... » read more

Servers And The Drive to DDR5


This IDC Technology Spotlight Study, sponsored by Rambus, discusses server demands on DRAM and different workloads. DRAM must dynamically adjust to the needs of these disparate workloads. The history of dynamic random-access memory (DRAM) is characterized by the ability of the technology to adapt to the increasingly specialized real-time memory requirements of the applications that utilize it. ... » read more

Hardware Architecture and Software Stack for PIM Based on Commercial DRAM Technology


Abstract: "Emerging applications such as deep neural network demand high off-chip memory bandwidth. However, under stringent physical constraints of chip packages and system boards, it becomes very expensive to further increase the bandwidth of off-chip memory. Besides, transferring data across the memory hierarchy constitutes a large fraction of total energy consumption of systems, and the ... » read more

What’s Ahead For DRAM, NAND?


For the last year, the semiconductor industry has been in the midst of a boom cycle. But if you look close enough, there are mixed signals in the market, especially in memory. Still, it’s a banner year for semiconductors. In total, the semiconductor market is expected to grow by 18.1% in 2021, according to Semico Research. That compares to 6.6% growth in 2020, according to Semico. Today... » read more

Servers And The Drive To DDR5


This IDC Technology Spotlight Study, sponsored by Rambus, discusses server demands on DRAM and different workloads. DRAM must dynamically adjust to the needs of these disparate workloads. The history of dynamic random-access memory (DRAM) is characterized by the ability of the technology to adapt to the increasingly specialized real-time memory requirements of the applications that utilize it. ... » read more

Lowering Energy Per Bit


Energy is emerging as a focal point in chip and system design, but solving energy-related issues needs to be dealt with on a much broader scale than design teams typically see. Energy is the amount of power consumed over a period of time to perform a given task, but reducing energy is a lot different than reducing power. It affects everything from operational costs and system performance to ... » read more

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