tag: dynamic power

Experts At The Table: FinFET Questions And Issues
By Ed Sperling - 11 Apr, 2013 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss the current state and future promise of finFETs, and the myriad challenges, with Ruggero Castagnetti, an LSI fellow; Barry Pangrle, senior power methodology engineer at Nvidia; Steve Carlson, group director of marketing at Cadence; and Mary Ann White, director of product marketing at Synopsys. What follows are excerpts ... » read more

Feel The (Low) Power
By Ed Sperling - 17 Sep, 2009 - Comments: 0

By Clive (Max) Maxfield When I designed my first ASIC way back in the mists of time (circa 1980), its power consumption was the last thing on my mind. You have to remember that we're talking about a device containing only about 2,000 equivalent gates implemented in a 5 micron technology. Also, I was designing this little scamp as a gate-register-level schematic using pencil and paper (I pr... » read more

Lower Power, Bigger Problems
By Ed Sperling - 13 May, 2009 - Comments: 0

By Ed Sperling Low power used to be an afterthought in semiconductor design, and it almost was never a consideration in verification or manufacturability. But at each new process node, the number of power considerations goes up as the line widths go down. To begin with, there are two basic types of power. The first is dynamic, which has been a consideration ever since batteries were added int... » read more

Minimizing Power Consumption In Next-Generation Mobile Devices
By Cheryl Ajluni - 13 Mar, 2009 - Comments: 0

By Cheryl Ajluni Today’s consumers continually demand ever more efficient and reliable means of mobile communication. At the same time, the wireless industry is evolving toward higher data rates and capacities. Both of these trends present a wealth of opportunity for innovative system engineers looking to design the next generation of mobile communication devices. They also pose some inter... » read more

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