Challenges Linger For EUV

By Mark LaPedus - 11 Nov, 2020 - Comments: 2

Semiconductor Engineering sat down to discuss lithography and photomask issues with Bryan Kasprowicz, director of technology and strategy and a distinguished member of the technical staff at Photronics; Harry Levinson, principal at HJL Lithography; Noriaki Nakayamada, senior technologist at NuFlare; and Aki Fujimura, chief executive of D2S. What follows are excerpts of that conversation. To vie... » read more

Mask/Lithography Issues For Mature Nodes

By Mark LaPedus - 22 Oct, 2020 - Comments: 0

Scramble For The White Space

By Bryon Moyer - 13 Oct, 2020 - Comments: 0

Chipmakers are pushing to utilize more of the unused portion of a design for different functions, reducing margin in the rest of the chip to more clearly define that white space. White space typically is used to relieve back-end routing congestion before all of the silicon area is used up. But a significant amount of space still remain unused. That provides an opportunity for inserting monit... » read more

eBeam Initiative Surveys Report Upbeat Photomask Market Outlook

By Jan Willis - 05 Oct, 2020 - Comments: 0

Every year, the eBeam Initiative conducts surveys that provide valuable insight into the key trends that are shaping the semiconductor industry. This year, industry luminaries representing 42 companies from across the semiconductor ecosystem participated in the 2020 eBeam Initiative Luminaries survey. 89% of respondents to the survey predict that photomask (mask) revenues in 2020 will stay the ... » read more

Finding Defects With E-Beam Inspection

By Mark LaPedus - 20 Aug, 2020 - Comments: 0

Several companies are developing or shipping next-generation e-beam inspection systems in an effort to reduce defects in advanced logic and memory chips. Vendors are taking two approaches with these new e-beam inspection systems. One is a more traditional approach, which uses a single-beam e-beam system. Others, meanwhile, are developing newer multi-beam technology. Both approaches have thei... » read more

Manufacturing Bits: June 8

By Mark LaPedus - 08 Jun, 2020 - Comments: 0

Maskless EUV lithography At this week’s 2020 EUVL Workshop, KJ Innovation will present more details about its efforts to develop a maskless extreme ultraviolet (EUV) lithography technology. Still in R&D, KJ Innovation’s maskless EUV technology involves a high-numerical aperture (high-NA) system with 2 million individual write beams. The 0.55 NA technology is targeted for direct-write l... » read more

Who’s Watching The Supply Chain?

By Ed Sperling - 17 Oct, 2019 - Comments: 0

Every company developing chips at the most advanced process nodes these days is using different architectures and heterogeneous processing and memory elements. There simply is no other way to get the kind of power/performance improvements needed to justify the expense of moving to a new process node. So while they will reap the benefits of traditional scaling, that alone is no longer enough. ... » read more

Challenges Grow For Finding Chip Defects

By Mark LaPedus - 19 Sep, 2019 - Comments: 5

Several equipment makers are developing or ramping up a new class of wafer inspection systems that address the challenges in finding defects in advanced chips. At each node, the feature sizes of the chips are becoming smaller, while the defects are harder to find. Defects are unwanted deviations in chips, which impact yield and performance. The new inspection systems promise to address the c... » read more

Manufacturing Bits: Sept. 17

By Mark LaPedus - 17 Sep, 2019 - Comments: 0

Full-chip inverse lithography D2S has developed new hardware and software that enables a long-awaited technology--full-chip masks using inverse lithography technology (ILT). For years, ILT has been a promising technology. ILT is a next-generation reticle enhancement technique (RET) that enables an optimal photomask pattern for both optical and extreme ultraviolet (EUV) lithography reticles.... » read more

New Imaging Tech Finds Buried Defects

By Shinsuke Mizuno - 23 May, 2019 - Comments: 0

By Shinsuke Mizuno and Vadim Kuchik Defects and contamination on the wafer can slow process development times and limit performance and yield. As chips get more complex, more defects can become buried within the increasing number of layers in the design. Finding and analyzing these buried defects is a major challenge for the industry, especially during the early learning cycles of new manufa... » read more

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