Challenges Grow For Finding Chip Defects

Costs are rising, and so is the time it takes to inspect a wafer.


Several equipment makers are developing or ramping up a new class of wafer inspection systems that address the challenges in finding defects in advanced chips.

At each node, the feature sizes of the chips are becoming smaller, while the defects are harder to find. Defects are unwanted deviations in chips, which impact yield and performance. The new inspection systems promise to address the challenges, but they are also more expensive than the previous tools, and chipmakers may need to buy a mix of them.

Used to find defects for both logic and memory chips in the fab, wafer inspection is split into two categories—optical systems and e-beam. Both types are often seen as complimentary, but there are some tradeoffs. Optical inspection tools are fast, but they have some resolution limits. Single beam, e-beam inspection systems have better resolution, but they are slower.

For years, e-beam inspection was used in R&D, while optical was (and still is) the workhorse tool in production fabs. Today, though, optical inspection is being stretched to the limit in some applications. So in select cases, chipmakers began to use e-beam inspection in the fab flow starting at 16nm/14nm.

Now, there are some new dynamics at play. Some vendors are developing a new class of multi-beam e-beam inspection systems. Using multiple beams, these systems promise to find tiny defects at faster speeds than today’s single e-beam tools.

They still aren’t ready for prime time, though. In fact, e-beam inspection of all types won’t replace optical anytime soon. And optical inspection isn’t standing still. “People like to portray these as one versus the other one,” said Dan Hutcheson, chief executive of VLSI Research. “But they are absolutely complementary. In fact, there is a whole triage of systems in the fab.”

Nonetheless, chipmakers are looking for new inspection solutions to meet the challenges at 10nm/7nm and beyond. Equipment makers have responded with new products or are working on them in R&D. Among the latest systems:

  • Applied Materials and KLA are ramping up new optical inspection systems for advanced nodes.
  • ASML and NuFlare are developing multi-beam e-beam inspection tools.

Hitachi High-Technologies and others also compete in the market. In terms of market size, optical inspection is bigger than e-beam. But amid an IC downturn, the overall process diagnostics tool market is expected to fall from $7.1 billion in 2018 to $5.7 billion in 2019, according to VLSI Research. In 2020, the market is expected to reach $5.9 billion, according to the firm. Process diagnostic tools include all types of inspection, metrology and related gear.

Defect challenges
Today’s advanced logic chips consist of three parts—the transistor, contacts and interconnects. The transistor resides on the bottom of the structure and serves as a switch. The interconnects, which reside on the top of the transistor, consist of tiny copper wiring schemes that transfer electrical signals from one transistor to another.

A middle-of-line layer connects the separate transistor and interconnect pieces using a series of tiny contact structures.

Fig. 1: Interconnect, contact and transistor at various nodes. Source: Applied Materials

Today, the industry is ramping up leading-edge chips at 10nm/7nm with 5nm in R&D. These devices incorporate finFET transistor structures. Unlike traditional planar transistors, which are 2D in nature, finFETs are 3D-like structures with better performance and lower leakage.

To make an advanced logic device, the wafer undergoes anywhere from 600 to 1,000 or more steps in the fab. Memory devices also undergo a multitude of steps in the fab.

In both logic and memory, defects can surface in chips during the manufacturing process, due to an unforeseen glitch in the flow. There are various types of physical defects in chips, such as bridges, protrusions and voids.

That’s where wafer inspection fits in. It finds those defects in chips. Optical inspection incorporates a database of what a die should look like. In the fab, the tool takes an image of a device and compares it to the database to determine whether it’s a good die or defective.

It’s more complicated than that, of course, especially for finFETs at 10nm/7nm and beyond. “The detection challenges for those are usually either very small or surface pattern defects, smaller than 30nm,” said Rafi Benami, vice president of the Inspection and Review Division at Applied Materials.

Memory is also challenging, particularly 3D NAND. “With 3D NAND, you have extreme high aspect ratios. This creates a whole new set of yield loss challenges. It requires new technologies,” Benami said.

In logic, meanwhile, the feature sizes are becoming smaller at each node. For example, a 7nm finFET transistor consists of a 57nm gate pitch and a 40nm metal pitch. A 5nm finFET may have a 48nm gate pitch with a 28nm metal pitch.

Then, as the feature sizes shrink, the critical defect size in the device also becomes smaller. “It’s a little harder to generalize these days because a node isn’t necessarily a full node,” said Chris Maher, senior director of marketing at KLA. “In general, we tend to look at it as a 30% shrink node over node in terms of size. It’s not that simple, though. Our signal is determined by the volume of the defect, and so in one dimension or two dimensions, the defect might shrink. But it may not shrink in the third dimension. In fact, it might even get bigger sometimes, or it might only shrink in the ‘z’ direction. That ends up being a problem for very low volume defects like very thin residues. That’s one of the industry’s challenges these days.”

If that’s not enough, it’s sometimes difficult to determine whether there is a defect on the chip. An inspection tool may detect what’s commonly called a nuisance. A nuisance is an irregularity on the wafer, but it’s not a defect of interest.

Dissecting the flow
With those challenges in mind, the industry requires more than one inspection tool type, at least for advanced nodes. It requires a myriad of systems in various steps.

Traditionally, wafer inspection tools are used in the following segments—engineering analysis; critical line monitoring; line monitoring and tool monitoring.

E-beam inspection is used for engineering analysis in the R&D group. E-beam, which examines a small part of a die, is used to find defects during the early stages of chip development. “In R&D and early ramp, we definitely deploy e-beam,” Applied’s Benami said. “There is where defect density is relatively high. Usually, the throughputs for e-beam are meeting the requirements for R&D.”

Critical line monitoring is conducted in the production fab. The goal is to find the most critical defects in patterned wafers. “You need a portfolio of different technologies here. You will need different optical and e-beam technologies. In addition to this portfolio, you need some integration,” Benami said.

Line monitoring, which is also done in the fab, also detects defects in wafers. In tool monitoring, the goal is to see if a piece of equipment is causing defects. For this, the equipment in question processes a wafer. Then, the inspection tool inspects the wafer to determine if the tool is meeting spec. Optical inspection is used for both line and tool monitoring.

Today, meanwhile, the lines are blurring between what’s used in R&D and the fab. At times, optical tools are used in R&D. E-beam is also being used in the fab, at least in some cases. For example, e-beam inspection is used to detect physical defects that are too small for optical.

“There’s a place for both,” said Mohan Iyer, head of marketing for the E-beam division at KLA. “It comes down to sensitivity to detect and being able to visualize and see those defects. That’s on one side. On the other side, there are other factors like coverage, speed and throughput.”

Generally, optical inspection makes sense to use in production because it’s faster and cost-effective. “Only in cases where you don’t have sensitivity to the defect, then you switch. People would tend to use e-beam. But they definitely won’t get the coverage that they would with optical,” Iyer said.

Economics also plays a role. For many device types, chipmakers won’t inspect every die on a wafer. It takes too long and is expensive. Instead, they might inspect the trouble spots in select dies, which may be sufficient.

There are exceptions to the rule. For example, the automotive industry is pushing for “zero defects” in chips. So these devices may require more inspection steps and die sampling than other types.

“Automotive requires a higher defect inspection sampling rate as well as harsher screening criteria. This is very different compared to consumer-grade products, which are inspected at lower sampling rates,” said Wenchi Ting, associate vice president at UMC. “Defects — especially those observed at the outgoing inspection stage — are often fall-on particles that do not affect the functionality, or the quality of the die the defects reside on. However, those could also be real defects, affecting transistors or the wiring on a microchip. The ‘zero-defect’ mantra says that we should classify any such defect die as a bad die, eliminating any possibility of these units going out to customers.”

There are other considerations. “Inspections also are carried out as part of the manufacturing process to measure parameters, such as thin-film thickness or width of patterned layers. Again, for automotive products, the specifications are often tightened compared to consumer-grade products. All these imply more work and more scraps when manufacturing automotive ICs, compared to the consumer-grade ones,” Ting said.

What is optical inspection?
In the optical inspection market, meanwhile, Applied Materials, Hitachi High-Technologies, KLA and others compete in this arena.

Optical inspection itself is split into two main segments, brightfield and darkfield. Darkfield inspection tools measure light reflected at a lower angle. Brightfield inspection, the workhorse technology in the fab, measures light at a higher angle. It uses broadband light to illuminate a wafer. Then, the light is collected and an image is digitized.

Optical inspection has a physical limit, although this depends on the system. Brightfield has sensitivities down to <5nm in SRAM, while darkfield is <15nm, according to data from ASML and others. Typically, these systems have a throughput of 1 or more wafers an hour, although this varies as well.

These figures are a moving target as vendors continue to make improvements in optical. Optical is also moving into new directions. For example, Applied’s existing wafer inspection tools are based on a combination of brightfield and greyfield techniques. Now, Applied has a new tool with more capabilities.

“With our latest tool, we actually use all three—brightfield, greyfield and darkfield,” Applied’s Benami said. “The difference is the illumination/collection angles. If we want a solution that is flexible and with wide application coverage, it needs to have all three.”

Meanwhile, KLA recently introduced two new optical wafer inspection systems—the 392x and 295x. The 392x is the more advanced system, while the 295x is the latest workhorse tool. Both systems incorporate advanced light sources and sensors. The systems also have wavelengths spanning from 190nm to 450nm. The wavelength plays a role in determining the sensitivity of a system, or its ability to detect defects. The decision to use a system at a given wavelength depends on the application.

KLA’s 295x is used for inspection in the front-end-of-the-line (FEOL) part of the fab, where the transistor is formed in devices. With wavelengths from 260nm to 450nm, this tool can meet most FEOL requirements, according to KLA.

With a wavelength down to 190nm, the more advanced 392x system is used in the backend-of-the-line (BEOL) part of the fab, where the interconnects, contact layers and metal layers are made in chips. In some cases, the 392x is used in the FEOL.

The BEOL structures are the most difficult to inspect. “The contact metals, such as metal 1 and metal 2, are very challenging,” KLA’s Maher said. “Those have always been some of the most challenging defects.”

Both KLA systems enable chipmakers to look for problems in specific regions in chips. For this, the system can map out and draw tiny blocks or “care areas” on the device. A care area is a specific location where a chipmaker wants to inspect with a given parameter.

Typically, a chipmaker would draw several care areas on a device. KLA’s previous tool allowed users to draw care areas down to 3 x 3 pixels. With KLA’s new systems, the tools can draw single-pixel care areas.

“It’s a game-changing ability in terms of optimizing the sensitivity of the system,” Maher said. “With the technology, we can say, ‘Inspect this pixel with this threshold because you are near a noisy area. We can also say, ‘Inspect this pixel with a lower threshold because you’re not near the noisy area.”

KLA’s systems also enables cell-to-cell inspection. All told, the technology enables 60 billion care areas per die. Every care area is registered to sub-pixel accuracy on every wafer.

What about e-beam?
Meanwhile, Applied and ASML compete in the e-beam inspection market. Others compete in a related field called e-beam defect review.

In e-beam inspection, electrons are generated in the system and penetrate the surface of a sample. Then the electrons scatter and bounce back to a detector in the tool, which provides information about the structure.

E-beam inspection tools can detect two types of signals — backscattered electrons (BSE) and secondary electrons. BSE are electrons that originate from deeper parts of the structure. Secondary electrons come from the surface.

E-beam inspection is used to find defects with sub-1nm sensitivities, according to ASML. It is also used for voltage-contrast defect applications, where it finds shorts, opens and voids in chips. In voltage-contrast applications, an external bias is applied to a device. Then the e-beam analyzes the variations in the image contrast of the structure to locate a problem.

This technology is used on a case-by-case basis in the fab. For example, it is used for defect detection for tiny cobalt contacts in the BEOL. It also might be used for finFETs. At each node, the fins in the finFET are becoming taller and narrower. At times, it’s difficult to locate the defects.

“Here, they can do is optical, e-beam inspection, and sometimes even two e-beam inspection technologies,” Applied’s Benami said. “In this specific case, since you have what we call a high aspect structure, you need a different e-beam technology between the top of the fins. So if you want something to see a defect in the bottom of the trench between the fins, you need what we call backscattered electron technology. And if you look on the top of the fin, you need secondary electrons.”

E-beam is useful in many apps, but it will never dominate the inspection landscape because it’s too slow. So in R&D, the industry has been working on multi-beam e-beam inspection. This, in turn, could help speed up the throughputs. So far, though, the technology isn’t ready for production.

In R&D, Hermes Microvision (HMI), an ASML company, has been working on a multi-beam inspection system. “The eScan 1000 is the first full multi-beam system with nine beams in a 3×3 configuration. The system will generate more accurate inspection data at higher speeds at the 5nm node and below,” said Gary Zhang, head of the marketing team at HMI. “Multi-beam will be used in R&D for discovery of systematic defects as small as 3 to 4nm. It also will be used in the production inline flow for certain applications where optical inspection is not effective.”

Meanwhile, NuFlare is developing a multi-beam inspection system, which is also in R&D. The first application is EUV mask inspection.

It is also being developed for wafer inspection. “It is targeted for 5nm wafer physical defect detection and EUV mask print check on the wafer,” said Nobutaka Kikuiri, director and general manager at NuFlare. “There is no solution with an optical tool (not enough sensitivity) or a single e-beam tool (not enough throughput).”

It remains to be seen when the multi-beam inspection tools will ship. The technology still faces several challenges. In multi-beam, for example, the electrons tend to disturb each other and so it’s difficult to control them.

For now, chipmakers will continue to use traditional e-beam and optical tools in the fab. They can handle most, if not all, tasks at 10nm/7nm and 5nm.

But some chipmakers are working on 3nm and beyond today. At that node and beyond, inspection will become even more challenging and expensive. That goes for the other tool types in the fab, as well. It doesn’t get any easier as new nodes are introduced.



Extremely useful information for migrators
to 5nm &3nm nodes.Thanks for the article!

Syed Hussain says:

Very informative article… kind of refresher on IC chip/wafer inspection and associated latest tools and techniques…
Thanks to the author . Hope to see many more such articles

Hong says:

Some comments on e-beam inspection:

secondary electron signal comes from sample surface. However, it can be used to detect buried defects through voltage contrast of conductive patterns, such as metal wires and metal contact plugs.

High-energy back-scattered electron signal can be used to detect buried defects. However, it can also be used to detect material contrast defects on the surface and sub-surface.

Steffen Capello says:

Based on this, will optical inspection even still play a role in the sub-5nm nodes?

Efi Rotem says:

very interesting and well written.
who is winning the e-beam inspection race?
is there data on actual resolution (or defect size), that e-beam tools from different vendors can achieve? (with tradeoff vs throughput – even better)

Leave a Reply

(Note: This name will be displayed publicly)