Finding Defects With E-Beam Inspection

New tools utilize different approaches, including ML, to boost performance.


Several companies are developing or shipping next-generation e-beam inspection systems in an effort to reduce defects in advanced logic and memory chips.

Vendors are taking two approaches with these new e-beam inspection systems. One is a more traditional approach, which uses a single-beam e-beam system. Others, meanwhile, are developing newer multi-beam technology. Both approaches have their place. The new systems are faster and offer better resolution than the previous equipment, but they also are more expensive and have some throughput limitations.

For years, chipmakers have relied on e-beam and optical inspection systems in advanced logic and memory fabs. Those technologies are complementary. Optical-based systems are fast and they are used to inspect an entire wafer for defects, but resolution is limited. E-beam has better resolutions, but it’s slower.

In an e-beam inspection system, electrons are generated within the tool, which then hit the surface of a die. The electrons scatter and bounce back to a detector, enabling it to find defects in chips. Compared with optical, e-beam inspection has significantly higher sensitivities — somewhere in the 1nm range. But it could take hours, if not days, to inspect a full wafer.

Because of that, e-beam inspection is used only to examine a small part of a die for defects, usually when optical can’t find certain defects. Often this happens in R&D, where problematic defects need to be located and rooted out. Then, in the fab, chipmakers use optical inspection tools to monitor and find chip defects in production. E-beam inspection is also used in fabs for select applications.

Optical inspection will remain the workhorse tool in fabs. But e-beam also plays an important role, and possibly an expanding one. “E-beam inspection is needed when you require high sensitivity and you need to find those difficult defects,” said Risto Puhakka, president of VLSI Research. “Let’s say you have a defect. You can’t recognize it with optical in a normal monitoring line. E-beam has its place here. You can run wafers through the system and figure out what’s going on. You do the root cause and cost analysis and all of that.”

While e-beam inspection is slow, next-generation tools promise to speed up the process, whether using a single- or multi-beam approach. Both types claim to find defects that other systems can’t detect. “I’m sure they are faster than the previous generation tools,” Puhakka said. “You can have tricks to make it faster. But it’s still slow.”

So the new e-beam tools won’t replace optical. E-beam inspection is still used “where you need high sensitivity, but the downside is that you have to accept a productivity loss,” Puhakka said.

Equipment makers are trying to change that perception, as evidenced by the activity in this market:

  • ASML recently shipped a new multi-beam inspection system.
  • KLA re-entered the e-beam inspection market with a new and faster single-beam tool.
  • NuFlare and Tasmit are separately developing new e-beam inspection systems.

Applied Materials, meanwhile, continues to offer its current single-beam e-beam inspection system.

Chip challenges
Amid a downturn in the IC market last year, the e-beam inspection market fell from $370 million in 2018 to $235 million in 2019, according to VLSI Research. In 2020, the e-beam inspection market is expected to rebound and reach about $300 million, according to the firm.

The overall wafer inspection market, including e-beam, optical and review tools, was a $3.04 billion business in 2019, according to VLSI Research. Of that figure, the optical inspection market is 11 times larger than the e-beam segment.

In the fab, all chips require wafer inspection. Take logic for example. At 28nm and above, chips incorporate planar transistors with larger feature sizes. Using various wafer inspection systems, chipmakers have little or no difficulties finding defects in planar devices.

Chips based on planar transistors are still widely used today at 28nm and above, but they actually reached their physical limit at 20nm. So starting in 2011, chipmakers migrated to finFET transistors at 22nm and 16nm/14nm. In finFETs, the control of the current is accomplished by implementing a gate on each of the three sides of a fin.

Fig. 1: FinFET vs. planar. Source: Lam Research

FinFETs provide more performance at lower power than planar transistors, but they are more expensive and harder to make in the fab. Consequently, process R&D and design costs have skyrocketed. Now, the cadence for a fully scaled node has extended from 18 to 30 months.

Today, leading-edge chipmakers are ramping up 7nm and 5nm finFET processes, with 3nm in R&D. The challenges are escalating at each node. The devices are becoming more complex with smaller feature sizes.

In a 28nm planar device, for example, a transistor may have a 117nm to 120nm contacted gate pitch (CPP) and a 90nm metal pitch, according to WikiChip, a technology site. In comparison, TSMC’s new 5nm finFET process features a 48nm CPP and a 30nm metal pitch, WikiChip reported. The CPP measures from one transistor’s gate contact to the gate contact on the adjacent device.

At 3nm and/or 2nm, chipmakers plan to migrate from finFETs to a gate-all-around transistor technology. One gate-all-around type, called nanosheet FETs, is a finFET on its side with a gate wrapped around it.

“For sure, 3nm will be more difficult than 5nm, which was more difficult than 7nm,” said Rick Gottscho, CTO of Lam Research. “There is a lot more complexity in a nanowire or nanosheet than in a finFET. There are new processes, and those are very challenging.”

Fig. 2: FinFET vs. nanosheet. Source: Imec

Nanosheets provide some price/performance benefits over finFETs, but there is only an incremental reduction in scaling. “The move from finFET to nanosheet is redefining the new era of how an increase in computer power and higher transistor densities will be achieved. It will be about changing the transistor architecture rather than making things smaller,” said Douglas Guerrero, senior technologist at Brewer Science.

The challenges aren’t limited to logic. “Whether it’s 3D NAND, DRAM or logic, everything is shrinking in the lateral direction in ‘x’ and ‘y,’ and then increasing in the ‘z’ direction. Everything is getting taller, deeper and smaller. Then, you have high-aspect ratio structures and very small regions where you have defects, and very small-size defects,” said Mohan Iyer, head of the E-beam Products Group at KLA.

That’s where wafer inspection fits in. These systems can find the problematic defects in chips. If the defects aren’t found, a chip may end up with poor yields or failures in the field.

Inspection flow
To capture the defects, chipmakers use e-beam and optical inspection tools. Both systems are used to find physical defects, such as voids, protrusions, and bridges in chips.

E-beam leverages the properties of electrons, while optical uses photons. Basically, an optical inspection system uses a broadband light source to illuminate a wafer. Then, the light is collected and an image is digitized, which helps find defects on the wafer.

In the fab, chipmakers use inspection systems for engineering analysis, critical line monitoring, and line monitoring.

E-beam inspection is used for engineering analysis in the R&D group. E-beam is used to find tiny and problematic defects during the early stages of chip development. Once those defects are rooted out and the chip meets spec, the device line moves to the fab.

Critical line monitoring is conducted in the fab. The goal is to find the most critical physical defects in patterned wafers. Line monitoring, which is also done in the fab, also detects defects in wafers. Both monitoring processes mainly use optical inspection. E-beam tools are also used sometimes.

“There’s a place for both,” KLA’s Iyer said. “It comes down to sensitivity to detect and being able to visualize and see those defects. That’s on one side. On the other side there are other factors like coverage, speed and throughput.”

Indeed, there are several tradeoffs. Optical inspection is fast, but it also has a physical limit. Optical has sensitivities down to <5nm in SRAM, according to experts.

Generally, e-beam inspection is used to detect physical defects that are too small for optical. E-beam inspection is also used for voltage-contrast defect applications. For this, an external bias is applied to a device. Then the e-beam analyzes the variations in the image contrast of the structure to locate shorts, opens and voids in chips.

Optical and e-beam inspection is sufficient for most chips. But at times, defects may go undetected, especially with advanced chips where the defect is buried or too small to find.

On top of that, the wafer inspection system also may detect a nuisance, which is an irregularity or false defect on the wafer. Generally, inspection systems can discern between a real defect and a nuisance. At times, though, the system struggles to differentiate between the two.

If a chipmaker can’t find the problem, it may resort to other techniques. For example, some may use a transmission electron microscope (TEM). A TEM provides three-dimensional images of a sample at high resolutions. But TEM is also a destructive technique. A chipmaker must cut a device and then put the structure in a TEM for inspection, making it impractical to use a TEM for in-line wafer inspection in the fab.

Next-gen e-beam inspection
So there is a gap. Chipmakers need a tool for hard-to-find, if not undetectable, defects. That’s where the next-generation e-beam inspection tools fit in. This equipment supposedly can find tiny and problematic defects that other systems can’t detect, and it’s faster than the previous systems.

Vendors are taking two approaches here—single beam and multi-beam. Single beam is the traditional approach, while multi-beam is newer. There is place for both types.

All e-beam inspection systems are complex with several moving parts, including an electron gun, column, detectors and a wafer stage. In operation, a wafer is placed in a system. Then, in the system, an electron gun generates electrons, which move down the column.

At that point, a stage moves a wafer to a given location. Then, the electrons hit a small part on a die. This in turn creates an image of the die. The image is compared to a database to determine whether it’s a defect.

A system generates two types of electrons, secondary or backscattered, to help identify defects in devices. Secondary electrons are low-energy electrons, which bounce back from a sample and provide surface information. Backscattered electrons penetrate deeper into the sample.

E-beam is too slow to inspect a full wafer, so it’s used to look at a small part of a die. The throughput is measured in mm² per hour. Optical tools are measured by wafers per hour.

The new e-beam inspection systems operate with many of these principles. But vendors have made some major modifications to improve the resolutions and throughputs.

KLA, for one, has re-entered the e-beam wafer inspection market with a faster single-beam tool. The system includes a new column design and detector architecture. It uses machine learning algorithms for defect detection.

KLA once participated in this market, but it exited the business around 2012. Last year, KLA introduced an e-beam review tool, which is different than e-beam inspection. Inspection tools look for defects, while review systems classify them.

Targeted for logic and memory, KLA’s new e-beam inspection system takes the technology to a different level. “There is no need to build yet another e-beam tool that does the exact same things that the other tools are doing today,” KLA’s Iyer said. “I am trying to find defects other people cannot find.”

It also addresses an issue that hampers traditional e-beam inspection. For example, using various knobs, an e-beam inspection tool can be adjusted to look for the smallest defects. In that case, though, the throughputs are slower. Then, the tool can be adjusted to go faster, but the resolutions are lower.

KLA’s tool overcomes those tradeoffs, enabling higher resolutions with better throughput. It’s still far slower than optical, but there are several ways to speed up e-beam inspection. One involves a knob called beam current density, which is a key spec in all e-beam tools.

Basically, the e-beam generates electrons and hits the target with a specific beam or spot size. Current density refers to how many electrons you have in your spot size. Generally, an end-user can determine the current density in a system, which comes with various tradeoffs.

Let’s say you want to find tiny defects. In a traditional system, the tool would be tuned with a lower current density for higher resolutions. Thus, the tool generates a beam with a smaller spot size.

“In traditional tools, you have a small spot for high resolution. To keep the spot size small, you use a lower current, which means fewer electrons in the spot. So you can have a small spot with a low beam current density that is sensitive, but it has a low throughput,” Iyer explained.

On the flip side, a traditional system can be adjusted with a higher current density. “The more current I have, the more electrons are put into the spot. Then, the spot gets larger,” Iyer said. “So, you can have a larger spot with more electrons and higher current, but with a lower sensitivity and higher throughput.”

With its new e-beam inspection system, though, KLA has found a way to overcome many of these issues using a new column design. The current in the system ranges from 200 picoamps to 40 nanoamps.

“Our beam goes down the column much faster to reach the sample. We put more electrons on the spot. We are able to pack more electrons into a much smaller spot and then use that for scanning. That gives us sensitivity and throughput at the same time,” Iyer said.

Besides current density, landing energy is another key knob in e-beam inspection. Landing energy refers to the amount of energy imparted on each electron before it hits a surface. The landing energy for traditional e-beam inspection tools ranges from 5KeV to 10KeV.

In comparison, KLA’s tool ranges from 200eV to 30KeV. The span of landing energy enables the tool to address a range of defect applications, including resists, high-aspect ratio structures and others.

Throughput also is improved. In a traditional system, the e-beam scans a part of the die. Then you move the stage, scan another part of the die, and acquire the image, which is slow process. In KLA’s tool, the system performs a 100µ x 100µ scan with a 1nm pixel. That translates into 10 billion pixels of information with a single scan without moving the stage. Still, the throughput is measured by mm² per hour.

“Scanning a full wafer with an e-beam tool will take a long time. I can do ‘care areas’ of very small regions within the die and across the wafer in a reasonable amount of time. Our goal is to get a wafer-level signature in a few hours, as opposed to a few days, weeks or months,” Iyer said.

Meanwhile, ASML recently shipped a multi-beam e-beam inspection system for 5nm and beyond. The company said this increases throughput by up to 600% compared with single-beam tools.

ASML also sells single-beam e-beam inspection systems. “As multi-beam inspection matures, it will gradually supplant single-beam inspection for many applications because of the benefit of higher throughput,” said Gary Zhang, vice president of product management at ASML. “For some applications, single-beam inspection will continue to be the better choice, such as physical inspection with back-scattered electron detection.”

ASML’s multi-beam tool simultaneously scans the die with 9 beams. “Simply put, the electrons from a single source are split into multiple beamlets at a fixed pitch using an aperture array. These beamlets are independently controlled by electro-optics modules fabricated with MEMS technology. A filter is used to bend the electrons emitted from the wafer surface into the secondary electron imaging module, where they are projected on a detector array with minimal cross talk,” Zhang said. “The system throughput is also helped by a high-speed stage shared with ASML lithography systems and a high-speed computational architecture to process the streams of data from the multiple beamlets in real time.”

There are some potential issues with this approach. Each beamlet may have a lower current density. In fact, the total current density is lower than a single-beam tool, so the scan times might be even longer in a multi-beam tool.

That doesn’t seem to be an issue yet. “Certainly, electron source power will become a constraint as the number of beamlets scale,” Zhang said. “Increasing the power of the electron source is a challenging engineering problem that ASML is working on. Possibly at a certain point, using multiple electron sources will be the preferred approach. That is still to be determined.”

All e-beam inspection suppliers are using machine learning to detect defects. Machine learning uses algorithms in systems to recognize patterns in data as well as to learn and make predictions about the information. In the fab, machine learning promises to provide faster and more accurate results in select areas, such as finding and classifying defects in chips.

Machine learning was first used for defect detection in the 1990s. “Machine learning back in those 90’s wasn’t deep learning. Machine learning back then was more about analyzing big data, doing mathematical analysis, and improving modeling by automating the scientific method,” said Aki Fujimura, CEO of D2S.

Recently, machine learning has taken off, thanks to a huge increase in compute power and better algorithms. “For deep learning training, GPUs generally are credited as the key enabler that allowed it to blossom,” Fujimura said. “That’s already happening for scientific computing applications like semiconductor manufacturing simulation and correction that D2S works on. But then deep learning also exploded because the ‘useful waste’ style of computing that’s needed for deep learning training. That is a perfect match for single-instruction multiple data (SIMD) computing that GPUs do tremendously well. Deep learning training enabled by GPUs is also the reason why automatic defect categorization and pattern recognition tasks are so much better now.”

For years, e-beam inspection has been a key tool in the fab. Today, with the defect challenges in chip manufacturing, chipmakers may have little choice but to buy the new e-beam tools.

“You may have an application where you want to have that type of measurement,” VSLI Research’s Puhakka said. “Then, you bite the bullet, spend the dollars and get the tools.”

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