Masks, Models And Alternative Lithography

By Jan Willis - 19 Apr, 2018 - Comments: 0

Every February an outstanding group of eBeam luminaries gathers at events hosted by the eBeam Initiative during the SPIE Advanced Lithography conference. It was our 10th annual lunch with standing room only attendance again this year. It’s an honor to get to know some of these very talented people. We started producing videos for the community over five years ago to share more of their storie... » read more

More Lithography/Mask Challenges (Part 2)

By Mark LaPedus - 17 Apr, 2018 - Comments: 3

Semiconductor Engineering sat down to discuss lithography and photomask technologies with Gregory McIntyre, director of the Advanced Patterning Department at [getentity id="22217" e_name="Imec"]; Harry Levinson, senior fellow and senior director of technology research at [getentity id="22819" comment="GlobalFoundries"]; Regina Freed, managing director of patterning technology at [getentity id="... » read more

Survey: Optimism Grows for EUV

By Mark LaPedus - 11 Sep, 2017 - Comments: 1

The optimism is growing for extreme ultraviolet (EUV) lithography in the market, according to a pair of new surveys released by the eBeam Initiative, which also revealed some new and surprising data about mask writing tools and other photomask technology. In one of the surveys from the [getentity id="22818" e_name="eBeam Initiative"], respondents revealed that they are more optimistic than e... » read more

Battling Fab Cycle Times

By Mark LaPedus - 16 Feb, 2017 - Comments: 9

The shift from planar devices to finFETs enables chipmakers to scale their processes and devices from 16nm/14nm and beyond, but the industry faces several challenges at each node. Cost and technical issues are the obvious challenges. In addition, cycle time—a key but less publicized part of the chip-scaling equation—also is increasing at every turn, creating more angst for chipmakers and... » read more

Inside Photomask Writing

By Mark LaPedus - 19 Jan, 2017 - Comments: 0

Hirokazu Yamada, a board member and the director of the Mask Lithography Division of NuFlare, sat down with Semiconductor Engineering to discuss photomask technology, e-beam mask writer trends and other topics. NuFlare is the world’s largest supplier of e-beam mask writers. What follows are excerpts of that conversation. SE: How does the [getkc id="265" kc_name="photomask"] market look in... » read more

More EUV Mask Gaps

By Mark LaPedus - 17 Nov, 2016 - Comments: 12

Extreme ultraviolet (EUV) lithography is at a critical juncture. After several delays and glitches, [gettech id="31045" comment="EUV"] is now targeted for 7nm and/or 5nm. But there are still a number of technologies that must come together before EUV is inserted into mass production. And if the pieces don’t fall into place, EUV could slip again. First, the EUV source must generate more ... » read more

Mask Maker Worries Grow

By Mark LaPedus - 22 Sep, 2016 - Comments: 0

Photomasks are becoming more complex and expensive at each node, thereby creating a number of challenges on several fronts. For one thing, the features on the [getkc id="265" kc_name="photomask"] are becoming smaller and more complex at each node. Second, the number of masks per mask-set are increasing as a result of multiple patterning. Third, it costs more to build and equip a new mask fab... » read more

Speeding Up Mask Production

By Mark LaPedus - 12 Sep, 2016 - Comments: 0

Chip production is becoming more complex and expensive at each node. As a result, chipmakers require a growing number of new manufacturing technologies to enable the next wave of devices at advanced nodes. In the fab, for example, the most obvious need is extreme ultraviolet ([gettech id="31045" comment="EUV"]) lithography. In addition, chipmakers also need a new class of atomic-level proces... » read more

Securing Chips During Manufacturing

By Ed Sperling - 07 Jul, 2016 - Comments: 0

David Lam, chairman of Multibeam, sat down with Semiconductor Engineering to talk about how next-gen lithography tools can be used to prevent cyber attacks and counterfeiting of hardware. SE: How did you get into the anti-counterfeiting business? Lam: About three years ago we were working with some customers that were troubled by the counterfeiting problem. We became aware of that sense o... » read more

Executive Insight: Aki Fujimura

By Mark LaPedus - 23 Jun, 2016 - Comments: 1

Aki Fujimura, chief executive of D2S, sat down with Semiconductor Engineering to look at the key issues in lithography and photomasks, as well as the changes taking place in the IC industry. What follows are excerpts of that conversation. SE: The semiconductor market is changing on several fronts. On one front, there is a wave of consolidation in the industry. And then there is a slowdown in... » read more

← Older posts Newer posts →

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?