tag: EDA

Continuous Integration For Digital Design
By Christian Skubich - 17 Dec, 2021 - Comments: 0

By Christian Skubich and Nico Peter In 2001, the Manifesto for Agile Software Development [1] laid the foundation for many modern software development processes. Today, 20 years later, agile methods are in widespread use in numerous domains. Out of the participants in the study Status Quo (Scaled) Agile 2020 [2], only 9% still relied on classic project management methods. One core element... » read more

The Return Of DAC In-Person
By Brian Bailey - 15 Dec, 2021 - Comments: 0

Apart from masked faces everywhere, you could be excused for not knowing that there was a pandemic going on. Sure, the numbers were down, the show floor was smaller, and most of the parties didn't happen, but everyone was so happy to be able to bump elbows with their colleagues. Buttons were available for attendees to show the level of comfort they had with various types of greetings, from "... » read more

Design Meets EDA: Gaps And Countermeasures In Analog/Mixed-Signal IC Design
By Fraunhofer IIS/EAS - 08 Dec, 2021 - Comments: 0

Along the path from specification to silicon, the design of analog/mixed-signal chips comprises a variety of challenges. They are of technological, methodological, organizational, communicational, and business nature. Additionally, large gaps are to be managed among the individual challenges. Still up to now, approaches such as the “four eye principle” are used even in industrial practice i... » read more

Missing Interposer Abstractions And Standards
By Brian Bailey - 29 Nov, 2021 - Comments: 0

The design and analysis of an SoC based on an interposer is not for the faint of heart today, but the industry is aware of the challenges and is attempting to solve them. Until that happens, however, it will be a technique that only large companies can deploy because they need to treat everything almost as if it were a single die. The construction of large systems uses techniques, such as ab... » read more

Structural Vs. Functional
By Brian Bailey - 23 Nov, 2021 - Comments: 0

When working on an article about PLM and semiconductors, I got to review a favorite topic from my days in EDA development – verification versus validation. I built extensive presentations around it and tried to persuade people within the EDA industry, as well as customers, about the advantages of doing a top-down functional modeling and analysis. The V diagram that everyone uses is flawed and... » read more

Advanced Packaging Shifts Design Focus To System Level
By Ann Mutschler - 23 Nov, 2021 - Comments: 0

Growing momentum for advanced packaging is shifting design from a die-centric focus toward integrated systems with multiple die, but it's also straining some EDA tools and methodologies and creating gaps in areas where none existed. These changes are causing churn in unexpected areas. For some chip companies, this has resulted in a slowdown in hiring of ASIC designers and an uptick in new jo... » read more

Raising The Bar With The Next Generation Of AI For Chip Design
By Synopsys - 22 Nov, 2021 - Comments: 0

The semiconductor industry is enjoying renewed growth despite chip shortages plaguing everything from cars to kitchen appliances. But while the chips themselves continue to get faster and smarter, the chip design process itself hasn’t changed that much in 20+ years. It typically takes 2-3 years to design a chip with a large engineering team and tens or hundreds of millions of dollars to get a... » read more

PPA(V): Performance-Per-Watt Optimization With Variable Operating Voltage
By Synopsys - 10 Nov, 2021 - Comments: 0

Performance-per-watt has emerged as one of the highest priorities in design quality, leading to a shift in technology focus and design power optimization methodologies. Variable operating voltage possess high potential in optimizing performance-per-watt results but requires a signoff accurate and efficient methodology to explore. Synopsys Fusion Design Platform, uniquely built on a singular RTL... » read more

What’s Missing For Designing Chips At The System Level
By Ed Sperling - 01 Nov, 2021 - Comments: 0

Semiconductor Engineering sat down to talk about design challenges in advanced packages and nodes with John Lee, vice president and general manager for semiconductors at Ansys; Shankar Krishnamoorthy, general manager of Synopsys' Design Group; Simon Burke, distinguished engineer at Xilinx; and Andrew Kahng, professor of CSE and ECE at UC San Diego. This discussion was held at the Ansys IDEAS co... » read more

Dealing With Market Shifts
By Brian Bailey - 28 Oct, 2021 - Comments: 1

Back in the days when I was in EDA development, I was taken in by the words of Clayton Christensen when he published "The Innovators Dilemma." He successfully introduced the technology world to the ideas of disruptive innovation. One of the key takeaways was that you should always be working to make your own successful products redundant, or someone else will do it for you. One tool I worked... » read more

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