tag: EDA

Current Problems Grow For Power Delivery
By Brian Bailey - 16 Oct, 2025 - Comments: 0

IR drop is becoming more problematic for a growing proportion of designs, an indication that the power delivery network (PDN) is not providing enough current to parts of the design when required. Unfortunately, there is no easy fix to this problem. In the past, when voltages were much higher, a small voltage droop didn't really matter. At the same time, wires were much thicker and presented ... » read more

Silicon IP Continues Steady Growth Path
By Ann Mutschler - 06 Oct, 2025 - Comments: 0

EDA and silicon IP revenue increased 8.6% to $5.089 billion in Q2 2025, up from $4.6855 billion in Q2 2024, according to the ESD Alliance. Total EDA revenue growth was assisted by impressive results in the CAE category, the largest tool sector, which showed 17.2% growth over Q2 2024. “It was another good quarter overall," said Walden C. Rhines, executive sponsor of the SEMI Electronic Desi... » read more

What Does Semiconductor Disruption Look Like?
By Brian Bailey - 25 Sep, 2025 - Comments: 2

When conducting interviews for my article on the incorporation of AI within EDA tools, Anand Thiruvengadam, senior director and head of AI product management at Synopsys, said, "AI has the potential to transform how customers do chip design. The entire EDA flow can be disrupted with AI." He is not alone in making this kind of statement. Each year, I do a predictions piece, and I ask about how A... » read more

AI Agents For UVM Generation: Challenges And Opportunities
By Kexun Zhang - 25 Sep, 2025 - Comments: 0

By Yuheng Tang and Kexun Zhang In the last two years, the role of AI tools in developers' workflows has rapidly expanded. What were once simple "code completion" engines have since evolved into agents that can read documentation, test their own code, and improve via self-reflection. While AI has already begun enhancing RTL design workflows, its exploration in verification remains in early st... » read more

The Limits Of AI’s Role In EDA Tools
By Brian Bailey - 25 Sep, 2025 - Comments: 0

The world has been inspired by generative AI models like ChatGPT. These are very applicable to things like copilots and agentic AI, but the adoption of these models into EDA tools is less obvious. What may be appropriate, and can AI make EDA tools faster or better? EDA has been enabling Moore's Law for the past 40 years, and that has required pushing the limits of many of the algorithms and ... » read more

Overview of Incorporating LLMs into EDA, With 3 Case Studies (TU Munich et al.)
By Technical Paper Link - 05 Sep, 2025 - Comments: 0

A new technical paper titled "Large Language Models (LLMs) for Electronic Design Automation (EDA)" was published by researchers at the Technical University of Munich, University of Stuttgart, New York University, and University of Siegen. Abstract "With the growing complexity of modern integrated circuits, hardware engineers are required to devote more effort to the full design-to-manufactu... » read more

3D-ICs In The Automotive Market: Breaking Barriers With AI-Driven EDA Tools
By Reela Samuel - 04 Sep, 2025 - Comments: 0

The automotive industry is experiencing a significant transformation as it adopts innovations like autonomous driving technologies and ultra-connected ecosystems. At the core of this change is a rising demand for compact, high-performance semiconductor solutions that can handle the increasing complexity of modern vehicle architecture. One promising development is three-dimensional integrated ci... » read more

Calibre 3DStress: Advanced Stress Analysis For Reliable 3D IC Design
By Siemens EDA - 03 Sep, 2025 - Comments: 0

As the industry transitions toward advanced 3D IC architectures and heterogeneous integration, managing thermo-mechanical stress is essential for product quality and long-term reliability. Calibre 3DStress enables design and packaging teams to simulate, analyze and disposition stresses imparted on the chip during or after the packaging process, ensuring that potential failure risks—such as wa... » read more

AI’s Value In Chip Design Depends On Data Availability
By Ed Sperling - 03 Sep, 2025 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss the advantages and challenges in using AI in designing chips, with Chuck Alpert, Cadence Fellow; Sathish Balasubramanian, head of product marketing and senior director for custom IC at Siemens EDA; Anand Thiruvengadam, senior director and head of AI product management at Synopsys; Sailesh Kumar, CEO of Baya Systems; Mehir ... » read more

Verification Fails To Keep Up
By Brian Bailey - 28 Aug, 2025 - Comments: 0

Experts at the table: Semiconductor Engineering sat down to discuss the state of functional verification with Mohan Dhene, director for architecture and design at Alphawave Semi; Andy Nightingale, vice president for product management and marketing at Arteris; Dinesha Rao, senior group director for software engineering at Cadence; Chris Mueth, new opportunities business manager at Keysight; Gor... » read more

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