tag: EDA

Shallow Clock Tree Pre-Estimation for Designing Clock Tree Synthesizable Verilog RTLs (Kyungpook National University)
By Technical Paper Link - 31 Oct, 2023 - Comments: 0

A technical paper titled “Shallow Clock Tree Pre-Estimation for Designing Clock Tree Synthesizable Verilog RTLs” was published by researchers at Kyungpook National University. Abstract: "Clock tree synthesis (CTS) is an important process in determining overall chip timing and power consumption. The CTS is also a time-consuming process for checking the clock tree. If the chip design and sp... » read more

Rethinking Design, Workflow For 3D
By Karen Heyman - 26 Oct, 2023 - Comments: 0

In the 3D world, where NAND has hundreds of layers and packages come in intricate stacks, fresh graduates and veteran engineers alike are being confronted with design challenges that require a rethinking of both classic designs and traditional workflows, but without breaking the laws of physics. “There are pockets of things that have been on 3D for quite some time,” said Kenneth Larson, ... » read more

Why Curvy Design Now? Less Change Than You Think And Manufacturable Today
By Jan Willis - 19 Oct, 2023 - Comments: 0

A curvilinear (curvy) chip, if magically made possible, would be smaller, faster, and use less power. Magic is no longer needed on the manufacturing side, as companies like Micron Technology are making photomasks with curvy shapes using state-of-the-art multi-beam mask writers today. Yet the entire chip-design infrastructure is based on the Manhattan assumption of 90-degree turns, even though i... » read more

Looking Forward To The New Chip Cycle
By Bob Smith - 19 Oct, 2023 - Comments: 0

Charles Shi, Principal and Senior Analyst at Needham & Company, LLC., remains upbeat about the EDA, IP and services business, or what SEMI refers to as the electronic system design (ESD) ecosystem. I recently spoke with Shi about his talk “Looking Forward to the New Chip Cycle” during the opening of the 2023 Design Automation Conference, collocated in July with SEMICON West in San Fra... » read more

EDA Revenue Up Again
By Ed Sperling - 17 Oct, 2023 - Comments: 0

The EDA industry reached $3.963 billion in revenue in Q2, boosted by a 17.6% increase in computer-aided engineering and a 17.2% increase in IP physical design and verification, according to a just-released ESD Alliance Electronic Market Data report. The overall growth was offset by an accounting change in the IP business, which resulted in a 11.6% decline to $1.255 billion, as well as some w... » read more

Applying Machine Learning to EDA, FPGA Design Automation Tools
By Technical Paper Link - 11 Oct, 2023 - Comments: 0

A technical paper titled “Application of Machine Learning in FPGA EDA Tool Development” was published by researchers at the University of Texas Dallas. Abstract: "With the recent advances in hardware technologies like advanced CPUs and GPUs and the large availability of open-source libraries, machine learning has penetrated various domains, including Electronics Design Automation (EDA). E... » read more

How Quickly Will Multi-Die Systems Change Semiconductor Design?
By Synopsys - 04 Oct, 2023 - Comments: 0

For many decades, semiconductor design and implementation has been focused on monolithic, ever-larger and more complex single-chip implementation. This system-on-chip approach is now changing for a variety of reasons. The new frontier utilizes many chips assembled in new ways to deliver the required form-factor and performance. Multi-die systems are paving the way for new types of semiconduc... » read more

LLM-Aided AI Accelerator Design Automation (Georgia Tech)
By Technical Paper Link - 28 Sep, 2023 - Comments: 0

A technical paper titled “GPT4AIGChip: Towards Next-Generation AI Accelerator Design Automation via Large Language Models” was published by researchers at Georgia Institute of Technology. Abstract: "The remarkable capabilities and intricate nature of Artificial Intelligence (AI) have dramatically escalated the imperative for specialized AI accelerators. Nonetheless, designing these accele... » read more

Industry Pressure Grows For Simulating Systems Of Systems
By Brian Bailey - 28 Sep, 2023 - Comments: 0

Most complex systems are designed in a top-down manner, but as the amount of electronic content in those systems increases, so does the pressure on the chip industry to provide high-level models and simulation capabilities. Those models either do not exist today, or they exist in isolation. No matter how capable a model or simulator, there never will be one that can do it all. In some cases,... » read more

What Happened To Portable Stimulus?
By Brian Bailey - 28 Sep, 2023 - Comments: 0

In June 2018, Accellera released the initial version of the Portable Test and Stimulus Standard (PSS), a new verification language that was slated to be the first new abstraction defined within EDA for a couple of decades. So what happened to it? Apart from a few updates at DVCon, there appears to be little talk about it today. However, the industry has its head down trying to make it work, ... » read more

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