tag: EDA

Best Options For Using AI In Chip Design
By Ed Sperling - 20 Aug, 2025 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss how and where AI can be applied to chip design to maximize its value, and how that will impact the design process, with Chuck Alpert, Cadence Fellow; Sathish Balasubramanian, head of product marketing and senior director for custom IC at Siemens EDA; Anand Thiruvengadam, senior director and head of AI product management at S... » read more

Re-Architecting AI For Power
By Brian Bailey - 14 Aug, 2025 - Comments: 0

The industry is becoming increasingly concerned about the amount of power being consumed by AI, but there is no simple solution to the problem. It requires a deep understanding of the application, the software and hardware architectures at both the semiconductor and system levels, and how all of this is designed and implemented. Each piece plays a role in the total power consumed and the utilit... » read more

Reliable Training Data Paramount To AI Model Success
By Ann Mutschler - 14 Aug, 2025 - Comments: 0

AI systems are increasingly being integrated into safety- and mission-critical applications ranging from automotive to health care and industrial IoT, stepping up the need for training data that is reliable, secure, and which is generated from trusted sources. AI activity is growing exponentially, as everybody tries to figure out how to apply it to their domain, application, or workload. In ... » read more

Agentic AI: Lots Of Little Black Boxes
By Ed Sperling - 07 Aug, 2025 - Comments: 0

AI is changing so quickly that it's not always clear how much of a security threat it poses for semiconductor design, and that uncertainty increases as AI agents are introduced into the mix. So far, the use of AI in chip design has been highly targeted. Most of what is included in design tools is some version of machine learning, bounded by tight control loops. EDA and IP vendors, large chip... » read more

Hallucination And Innovation At DAC
By Brian Bailey - 31 Jul, 2025 - Comments: 0

At DAC this year, I had the pleasure of moderating an intimate chat between Alon Shtepel, senior director for ASIC at Micron, and Abhi Kolpekwar, vice president and general manager for digital verification technology at Siemens EDA. The assigned topic was generative AI in design and verification, with the more provocative subtitle asking if we are hallucinating or innovating? L-R: Brian ... » read more

Multi-Modal AI In EDA Development Flows
By Brian Bailey - 31 Jul, 2025 - Comments: 0

RTL coding is a critical step in the development of semiconductors, but many would argue it is not the most difficult. Things become a lot more complex as you get closer to implementation, and as the system context becomes larger than can be comprehended by text alone. In both cases, layout, timing, power, and many other factors come into play, but none is as easily represented by text, and the... » read more

AI, Product Lifecycle Management, Market Dynamics: Q&A With Jay Vleeschhouwer Of Griffin Securities 
By Bob Smith - 24 Jul, 2025 - Comments: 0

In the world of EDA, Jay Vleeschhouwer, managing director of software research at Griffin Securities, needs no introduction. His presentation on the State of EDA is standing room only at the yearly Design Automation Conference (DAC). He recently agreed to a discussion with me where we talked about AI and EDA, an interesting development with product lifecycle management and global dynamics af... » read more

Chiplet Ecosystem Slowly Emerges
By Brian Bailey - 23 Jul, 2025 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss progress and remaining challenges for designing with chiplets with Mark Kuemerle, vice president of technology for Marvell; Letizia Giuliano, vice president for product marketing and management at Alphawave Semi; Hee-Soo Lee, HSD segment lead for Keysight; Mick Posner, senior product group director for Cadence’s Compute S... » read more

Largest High-Quality Verilog Dataset for LLM Fine-Tuning (Univ. of Florida)
By Technical Paper Link - 22 Jul, 2025 - Comments: 0

A new technical paper titled "VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generation" was published by researchers at the University of Florida. Abstract "Large Language Models (LLMs) are gaining popularity for hardware design automation, particularly through Register Transfer Level (RTL) code generation. In this work, we examine the curr... » read more

AI In Chip Design: Tight Control Required
By Ed Sperling - 16 Jul, 2025 - Comments: 0

Executive Outlook: Semiconductor Engineering sat down with a panel of experts to talk about what's needed to effectively leverage AI, who benefits from it, and where software-defined hardware works best, with Bill Mullen, Ansys fellow; John Ferguson, senior director of product management at Siemens EDA; Chris Mueth, senior director of new markets and strategic initiatives at Keysight; Albert Ze... » read more

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