tag: EDA

Hallucination And Innovation At DAC
By Brian Bailey - 31 Jul, 2025 - Comments: 0

At DAC this year, I had the pleasure of moderating an intimate chat between Alon Shtepel, senior director for ASIC at Micron, and Abhi Kolpekwar, vice president and general manager for digital verification technology at Siemens EDA. The assigned topic was generative AI in design and verification, with the more provocative subtitle asking if we are hallucinating or innovating? L-R: Brian ... » read more

Multi-Modal AI In EDA Development Flows
By Brian Bailey - 31 Jul, 2025 - Comments: 0

RTL coding is a critical step in the development of semiconductors, but many would argue it is not the most difficult. Things become a lot more complex as you get closer to implementation, and as the system context becomes larger than can be comprehended by text alone. In both cases, layout, timing, power, and many other factors come into play, but none is as easily represented by text, and the... » read more

AI, Product Lifecycle Management, Market Dynamics: Q&A With Jay Vleeschhouwer Of Griffin Securities 
By Bob Smith - 24 Jul, 2025 - Comments: 0

In the world of EDA, Jay Vleeschhouwer, managing director of software research at Griffin Securities, needs no introduction. His presentation on the State of EDA is standing room only at the yearly Design Automation Conference (DAC). He recently agreed to a discussion with me where we talked about AI and EDA, an interesting development with product lifecycle management and global dynamics af... » read more

Chiplet Ecosystem Slowly Emerges
By Brian Bailey - 23 Jul, 2025 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss progress and remaining challenges for designing with chiplets with Mark Kuemerle, vice president of technology for Marvell; Letizia Giuliano, vice president for product marketing and management at Alphawave Semi; Hee-Soo Lee, HSD segment lead for Keysight; Mick Posner, senior product group director for Cadence’s Compute S... » read more

Largest High-Quality Verilog Dataset for LLM Fine-Tuning (Univ. of Florida)
By Technical Paper Link - 22 Jul, 2025 - Comments: 0

A new technical paper titled "VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generation" was published by researchers at the University of Florida. Abstract "Large Language Models (LLMs) are gaining popularity for hardware design automation, particularly through Register Transfer Level (RTL) code generation. In this work, we examine the curr... » read more

AI In Chip Design: Tight Control Required
By Ed Sperling - 16 Jul, 2025 - Comments: 0

Executive Outlook: Semiconductor Engineering sat down with a panel of experts to talk about what's needed to effectively leverage AI, who benefits from it, and where software-defined hardware works best, with Bill Mullen, Ansys fellow; John Ferguson, senior director of product management at Siemens EDA; Chris Mueth, senior director of new markets and strategic initiatives at Keysight; Albert Ze... » read more

Silicon IP Revenue Spikes
By Ed Sperling - 15 Jul, 2025 - Comments: 0

EDA and silicon IP revenue grew 12.8% in Q1 2025, totaling $5.098 billion compared to $4.522 billion in the same period last year, but the real story was on the IP side, surging 29.6% year-over-year to $1.577 billion. Drilling deeper into those numbers, revenue for non-reporting IP companies — predominantly Arm — jumped 34.1% YoY to $1.031 billion. That was positive news for the IP marke... » read more

Cognichip: Using AI To Speed Complex Chip Design
By Ed Sperling And Emma Riverso - 15 Jul, 2025 - Comments: 1

AI software innovation is accelerating, while the chip design process is struggling to keep pace due to rising complexity and physical constraints. The big challenge now is how to close that gap. The solution is at least as complex as the hardware design. It requires much greater reuse of IP, along with portions of existing designs, so that not everything needs to be created from scratch. AI... » read more

EDA Startups At DAC 2025
By Jesse Allen - 09 Jul, 2025 - Comments: 0

The 62nd DAC showcased numerous new exhibitors in 2025, including tool and IP providers, design services firms, and component marketplaces. New EDA startups, in particular, had a robust showing, with entrepreneurial engineers seeking to tackle the increasingly complex challenges facing modern chip design with fresh approaches. AI was a strong theme throughout the show, with companies of all ... » read more

LLM-Powered Automatic VLSI Design Flow Tuning Framework
By Technical Paper Link - 08 Jul, 2025 - Comments: 0

A new technical paper titled "CROP: Circuit Retrieval and Optimization with Parameter Guidance using LLMs" was published by researchers at Duke University and Synopsys. Abstract "Modern very large-scale integration (VLSI) design requires the implementation of integrated circuits using electronic design automation (EDA) tools. Due to the complexity of EDA algorithms, the vast parameter space... » read more

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