Wire Bond Electrical Structural Test Methodologies

By Keysight - 28 Aug, 2024 - Comments: 0

Wire bonding, a foundational process in microelectronics, is essential to establishing a robust and low-resistance electrical connection between semiconductor chips and their respective packages or, in the case of multi-chip modules, between different chips. This intricate process ensures the device's functionality, reliability, and overall performance. Wire bonding faces several challenges ... » read more

Complete Reliability Verification For Multiple-Power-Domain Designs

By Siemens EDA - 09 Nov, 2022 - Comments: 0

With increasing design complexity and a heightened focus on reliability at all levels of integrated circuit (IC) design from intellectual property (IP) to full-chip, accurate and full verification coverage of the different reliability concerns within an IC design is essential. Designs containing multiple power domains add more complexity to reliability verification with the need to validate int... » read more

Improving Circuit Reliability

By Ed Sperling - 03 Mar, 2020 - Comments: 0

Carey Robertson, product marketing director at Mentor, a Siemens Business, examines reliability at advanced and mainstream nodes, particularly in automotive and industrial applications, what’s driving growing concern about the reliability and fidelity of analog circuits, and the impact of running circuits for longer periods of time under different voltage and environmental conditions. » read more

How Chips Age

By Ed Sperling - 20 Jan, 2020 - Comments: 1

Andre Lange, group manager for quality and reliability at Fraunhofer IIS’ Engineering of Adaptive Systems Division, talks about circuit aging, whether current methods of predicting reliability are accurate for chips developed at advanced process nodes, and where additional research is needed. » read more

Aging In Advanced Nodes

By Ann Mutschler - 17 Sep, 2018 - Comments: 0

Semiconductor Engineering sat down to discuss design reliability and circuit aging with João Geada, chief technologist for the semiconductor business unit at ANSYS; Hany Elhak, product management director, simulation and characterization in the custom IC and PCB group at Cadence; Christoph Sohrmann, advanced physical verification at Fraunhofer EAS; Magdy Abadir, vice president of marketing at ... » read more

Design Rule Complexity Rising

By Ed Sperling - 19 Apr, 2018 - Comments: 0

Variation, edge placement error, and a variety of other issues at new process geometries are forcing chipmakers and EDA vendors to confront a growing volume of increasingly complex, and sometimes interconnected design rules to ensure chips are manufacturable. The number of rules has increased to the point where it's impossible to manually keep track of all of them, and that has led to new pr... » read more

Tech Talk: Electrical Overstress

By Ed Sperling - 12 Apr, 2018 - Comments: 0

ANSYS Chief Technologist João Geada talks about electrical overstress and circuit aging and how what it means for automotive electronics. https://youtu.be/4bjdr0uvWG4 » read more

Multiphysics Reliability Signoff For Next-Gen Auto Electronics Systems

By Annapoorna Krishnaswamy - 12 Mar, 2018 - Comments: 0

The automotive industry is in the midst of a sea change. Growing market needs for electrification, connectivity on the go, advanced driver assistance systems, and ultimately the goal of autonomous driving, are creating newer requirements and greater challenges. A chassis on four wheels is now fitted with cameras, radar and other sensors, which will be the eyes of the driverless car, as well as ... » read more

Turning Down The Voltage

By Ann Mutschler - 08 Feb, 2018 - Comments: 0

Designers of large, advanced-node SoCs are grappling with a number of pressures in the quest to achieve the optimal performance and power of their designs. This has turned into a challenging balancing act between using less power, especially for consumer technologies, while also providing the same or greater performance and increased functionality. [getkc id="108" kc_name="Power"] and perfor... » read more

How Reliable Are FinFETs?

By Ann Mutschler - 16 Aug, 2017 - Comments: 1

Stringent safety requirements in the automotive and industrial sectors are forcing chipmakers to re-examine a number of factors that can impact reliability over the lifespan of a device. Many of these concerns are not new. Electrical overstress (EOS), electrostatic discharge (ESD) and [getkc id="160" kc_name="electromigration"] (EM) are well understood, and have been addressed by EDA tools f... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?