Managing EMI in High-Density Integration


The relentless drive for higher performance and increased functional integration has ushered in new challenges for managing electromagnetic interference (EMI) in densely packed mixed-signal environments. Integrating analog, RF, and digital circuits into a single system-on-chip (SoC) or advanced package requires solutions that reduce system size and improve performance. However, this tight in... » read more

Research Bits: November 14


Solid-state thermal transistor for heat management Researchers from University of California Los Angeles created a stable and fully solid-state thermal transistor that uses an electric field to control a semiconductor device’s heat movement. It is compatible with integrated circuits in semiconductor manufacturing processes. The team’s design incorporates the field effect on charge dynamics... » read more

Reducing Noise Issues In Microcontroller Systems: Part 1


In my ideal digital world, of which I often dream, signal voltage margins are always positive, signal timing margins are always positive, power supply voltages are always within the operating voltage range, and our environment is completely benign. Unfortunately, none of us live in this ideal world, no matter how much I would like to. The real world is dirty and noisy, and the power distribu... » read more

Research Bits: Feb. 6


Pillars for chiplet integration Researchers from the Tokyo Institute of Technology proposed a new chiplet integration technology called Pillar-Suspended Bridge (PSB), which they say is a simpler method of chip-to-chip connection compared to silicon interposers and redistribution layers. In the PSB, only a pillar-shaped metal structure called a "MicroPillar" is interposed at the connection b... » read more

EMC Pre-Compliance Fundamentals


Once you’ve designed your electronic product, it’s time to release it to market, right? Well, not exactly. As with any product development, you need to first test the device you’re designing to validate that it behaves as expected. One such important test that all electronic devices must eventually pass are EMI (electromagnetic interference) compliance tests. Passing EMI tests d... » read more

Electromagnetic Simulation And 3D-IC Interposers


By Matt Commens, Juliano Mologni, and Pete Gasperini Today’s 3D integrated circuit (3D-IC) technology is the culmination of 40 years of research in universities and laboratories scattered across the globe. Beginning with dynamic random-access memory (DRAM) deployments that appeared on the market a decade ago, 3D-IC has since expanded its reach. It is now decisively beginning to achieve the... » read more

Parasitic Characterization Comes To Power Design Simulation


Two power design challenges are taking teams into unfamiliar territory. Wide bandgap (WBG) semiconductors target greater efficiency and density. Stricter EMI compliance regulations now come standard in mission-critical industries. Power design practices are still catching up. Simulation often takes a back seat to respinning hardware prototypes until success. What’s missing that could make sim... » read more

PCB Design Rules For Wiring And Crosstalk


Today’s electronic devices market demands miniaturized printed circuit boards (PCBs) with a multitude of high-speed functions integrated on a single board. This causes the designers to have traces routed very close to each other to optimize packaging and space. This proximity may cause unintentional coupling of electromagnetic fields, a phenomenon which we know by the name of crosstalk (see f... » read more

PCB Design Rules For Electromagnetic Compatibility


When it comes to electromagnetic interference (EMI) and printed circuit boards (PCBs), rules are not meant to be broken. Following some simple guidelines for electromagnetic compatibility when designing PCBs will save time and costs. Simulation software can help. All high-speed signals on a PCB should be referenced to a solid plane. A current flowing in any trace on a PCB must complete the e... » read more

Week In Review: Design, Low Power


Tools & IP Cadence debuted System-Level Verification IP (System VIP), a suite of tools and libraries for automating SoC testbench assembly, bus and CPU traffic generation, cache-coherency validation, and system performance bottleneck analysis. Tests created using the System VIP solution are portable across Cadence simulation, emulation and prototyping engines and can also be extended to po... » read more

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