How To Deal With Electromigration

By Katherine Derbyshire - 02 Mar, 2015 - Comments: 8

The replacement of aluminum with copper interconnect wiring, first demonstrated by IBM in 1997, brought the integrated circuit industry substantial improvements in both resistance to electromigration and line conductivity. Copper is both a better and more stable conductor than aluminum. Difficult though the transition was, it helped extend device scaling for another eighteen years (and counting... » read more

First Look: 10nm

By Ed Sperling - 29 Jan, 2015 - Comments: 6

As the semiconductor industry begins grappling with mass production at 14/16nm process nodes, work is already underway at 10nm. Tools are qualified, IP is characterized, and the first test chips are being produced. It's still too early for production, of course—perhaps three years too early—but there is enough information being collected to draw at least some impressions about just how toug... » read more

Signal Integrity Issues

By Ed Sperling - 21 Jan, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss signal integrity with Rob Aitken, research fellow at [getentity id="22186" comment="ARM"]; PV Srinivas, senior director of engineering for the Place & Route Division of [getentity id="22017" e_name="Mentor Graphics"]; and Bernard Murphy, chief technology officer at [getentity id="22026" e_name="Atrenta"]. What follows are excerpts of that conver... » read more

IP Design Essentials For Reliability And SoC Integration

By Annapoorna Krishnaswamy - 15 Jan, 2015 - Comments: 0

IP is integral to every SoC design. The need for ubiquitous connectivity has pushed the threshold for content in SoCs even beyond the tenets of Moore’s Law. Technology scaling has not only enabled the delivery of increased performance and reduced power, but also rich content through the integration of a wide range of IPs such as radio devices, CMOS image sensors, MEMs, etc., into a single ... » read more

Why Is My Device Better Than Yours?

By Ed Sperling - 23 Oct, 2014 - Comments: 0

Differentiation is becoming a big problem in the semiconductor industry with far-reaching implications that extend well beyond just chips. The debate over the future of [getkc id="74" comment="Moore's Law"] is well known, but it's just one element in a growing list that will make it much harder for chip companies, IP vendors and even software developers to stand out from the pack. And withou... » read more

Optimizing Analog For Power At Advanced Nodes

By Ann Mutschler - 09 Oct, 2014 - Comments: 0

As any engineering manager will tell you, analog and digital engineers seem like they could be from different planets. While this has changed somewhat over time, [getkc id="52" comment="analog"] is still something of a mystery to many in [getkc id="81" kc_name="SoC"] design teams. Throw power management into the mix and things really get interesting. Improvements in analog/mixed-signal tools... » read more

The Week In Review: Design

By Ed Sperling - 08 Aug, 2014 - Comments: 0

Tools Cadence rolled out a custom power integrity tool for dealing with transistor-level electromigration and IR drop with SPICE-level accuracy. It works in conjunction with the company’s existing power integrity tool for cell-level power signoff. Open-Silicon established a high-speed SerDes technology center of excellence to speed design and production of ASICs using high-speed serial co... » read more

Changing The Meaning Of Sign-Off

By Muhammad Zakir - 07 Aug, 2014 - Comments: 0

Chip development teams are faced with an ever-increasing number of power integrity and reliability challenges these days, especially as designs adopt FinFET technology. Even those with the most thorough sign-off checks often encounter unexpected surprises that quickly turn into tape-out hurdles, or worse yet, extensive re-design. The best way to avoid this scenario and ensure a smoother sign-of... » read more

IP And FinFETs At Advanced Nodes

By Ed Sperling - 10 Jul, 2014 - Comments: 2

Semiconductor Engineering sat down to discuss IP and finFETs at advanced nodes with Bernard Murphy, CTO of Atrenta; Warren Savage, president and CEO of IPextreme; Aveek Sarkar, vice president of engineering and product support at Ansys-Apache; Randy Smith, vice president of marketing at Sonics. What follows are excerpts of that conversation. SE: As we push into the next nodes, we’ve got a ... » read more

FinFET Based Designs: Reliability Verification Implications

By Aveek Sarkar - 10 Jul, 2014 - Comments: 1

Over the past few months, I’ve discussed various challenges associated with finFET-based designs. We all know that finFET devices enable design teams to operate their chips at significantly lower supply voltages with a very tight control on leakage current. But to control the overall power within a tight power budget, the challenge shifts to how the logic design is managed such that the overa... » read more

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Knowledge Centers
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