Reducing Advanced Packaging Costs

By Ed Sperling - 09 Jan, 2019 - Comments: 0

Semiconductor Engineering sat down with Chenglin Liu, director of package engineering at Marvell; John Hunt, senior director of engineering at ASE; Eric Tosaya, senior director of package manufacturing at eSilicon; and Juan Rey, vice president of engineering for Calibre at Mentor, a Siemens Business. What follows are excerpts of that discussion, which was held in front of a live audience at MEP... » read more

PGIREM: Reliability-Constrained IR Drop Minimization and Electromigration Assessment of VLSI Power Grid Networks using Cooperative Coevolution

By Technical Paper Link - 31 Dec, 2018 - Comments: 0

Abstract "Due to the resistance of metal wires in power grid network, voltage drop noise occurs in the form of IR drop which may change the output logic of underlying circuits and may affect the reliability performance of a chip. Further, it is necessary to handle different reliability constraints while designing a robust power grid network for a chip. Any violation of such constraints may inc... » read more

Containing Design Complexity With POP IP

By Kelvin Low - 16 Nov, 2018 - Comments: 0

About 25 years ago, Carver Mead, one of the pioneers of VLSI design, told a technical audience then grappling with the complexities of quarter-micron design that he could see an evolutionary path to about 130nm, but after that point, the picture blurred. Flash forward to the present and we’re manufacturing SoCs at 7nm, and the output is truly amazing devices powering applications we and Me... » read more

Carmakers To Chipmakers: Where’s The Data?

By Ed Sperling And Susan Rambo - 24 Oct, 2018 - Comments: 0

The integration of electronics into increasingly autonomous vehicles isn't going nearly as smoothly as the marketing literature suggests. In fact, it could take years before some of these discrepancies are resolved. The push toward full autonomy certainly hasn't slowed down, but carmakers and the electronics industry are approaching that goal from very different vantage points. Carmakers and... » read more

Reliability, Machine Learning And Advanced Packaging

By Ed Sperling - 11 Oct, 2018 - Comments: 0

Semiconductor Engineering sat down to discuss reliability, resilience, machine learning and advanced packaging with Rahul Goyal, vice president in the technology and manufacturing group at Intel; Rob Aitken, R&D fellow at Arm; John Lee, vice president and general manager of the semiconductor business unit at ANSYS; and Lluis Paris, director of IP portfolio marketing at TSMC. What follows ar... » read more

Aging In Advanced Nodes

By Ann Mutschler - 17 Sep, 2018 - Comments: 0

Semiconductor Engineering sat down to discuss design reliability and circuit aging with João Geada, chief technologist for the semiconductor business unit at ANSYS; Hany Elhak, product management director, simulation and characterization in the custom IC and PCB group at Cadence; Christoph Sohrmann, advanced physical verification at Fraunhofer EAS; Magdy Abadir, vice president of marketing at ... » read more

Minimizing Chip Aging Effects

By Brian Bailey - 13 Sep, 2018 - Comments: 2

Aging kills semiconductors, and it is a growing problem for an increasing number of semiconductor applications—especially as they migrate to more advanced nodes. Additional analysis and prevention methods are becoming necessary for safety critical applications. While some aspects of aging can be mitigated up front, others are tied to the operation of the device. What can an engineering tea... » read more

Chip Aging Becomes Design Problem

By Brian Bailey - 09 Aug, 2018 - Comments: 9

Chip aging is a growing problem at advanced nodes, but so far most design teams have not had to deal with it. That will change significantly as new reliability requirements roll out across markets such as automotive, which require a complete analysis of factors that affect aging. Understanding the underlying physics is critical, because it can lead to unexpected results and vulnerabilities. ... » read more

5nm Design Progress

By Ann Mutschler - 17 Jul, 2018 - Comments: 1

Activity surrounding the 5nm manufacturing process node is quickly ramping, creating a better picture of the myriad and increasingly complex design issues that must be overcome. Progress at each new node after 28nm has required an increasingly tight partnership between the foundries, which are developing new processes and rule decks, along with EDA and IP vendors, which are adding tools, met... » read more

Dealing With Resistance In Chips

By Mark LaPedus - 21 Jun, 2018 - Comments: 2

Chipmakers continue to scale the transistor at advanced nodes, but they are struggling to maintain the same pace with the other two critical parts of the device—the contacts and interconnects. That’s beginning to change, however. In fact, at 10nm/7nm, chipmakers are introducing new topologies and materials such as cobalt, which promises to boost the performance and reduce unwanted resist... » read more

← Older posts Newer posts →

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: electromigration