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Legacy Tools, New Tricks: Optical 3D Inspection


Stacking chips is making it far more difficult to find existing and latent defects, and to check for things like for things like die shift, leftover particles from other processes, co-planarity of bumps, and adhesion of different materials such as dielectrics. There are several main problems: Not everything is visible from a single angle, particularly when vertical structures are used; ... » read more

Nanosheet FETs Drive Changes In Metrology And Inspection


In the Moore’s Law world, it has become a truism that smaller nodes lead to larger problems. As fabs turn to nanosheet transistors, it is becoming increasingly challenging to detect line-edge roughness and other defects due to the depths and opacities of these and other multi-layered structures. As a result, metrology is taking even more of a hybrid approach, with some well-known tools moving... » read more

3D NAND Metrology Challenges Growing


3D NAND vendors face several challenges to scale their devices to the next level, but one manufacturing technology stands out as much more difficult at each turn—metrology. Metrology, the art of measuring and characterizing structures, is used to pinpoint problems and ensure yields for all chip types. In the case of 3D NAND, the metrology tools are becoming more expensive at each iteration... » read more

Measuring Atoms And Beyond


David Seiler, chief of the Engineering Physics Division within the Physical Measurement Laboratory at the National Institute of Standards and Technology (NIST), sat down with Semiconductor Engineering to discuss the current and future directions of metrology. NIST, a physical science laboratory, is part of the U.S. Department of Commerce. What follows are excerpts of that conversation. SE: W... » read more

Optical Metrology Solutions For 10nm Films Process Control Challenges


By Sridhar Mahendrakar (a), Alok Vaida (a), Kartik Venkataraman (b), Michael Lenahan (a), Steven Seipp (a), Fang Fanga (a), Shweta Saxena (a), Dawei Hu (b), Nam Hee Yoon (b), Da Song (b), Janay Camp (b), Zhou Ren (b). [a: GlobalFoundries; b:KLA-Tencor] Controlling thickness and composition of gate stack layers in logic and memory devices is critical to ensure transistor performance meets r... » read more

Gaps In Metrology Could Impact Yield


For some time, chipmakers have been developing new and complex chip architectures, such as 3D NAND, finFETs and stacked die. But manufacturing these types of chips is no simple task. It requires a robust fab flow to enable new IC designs with good yields. In fact, yield is becoming a more critical part of the flow. Yield is a broad term that means different things to different parts of the ... » read more