Multi-Layer Processing Boosts Inference Throughput/Watt

By Geoff Tate - 15 Apr, 2019 - Comments: 0

The focus in discussion of inference throughput is often on the computations required. For example, YOLOv3, a power real time object detection and recognition model, requires 227 BILLION MACs (multiply-accumulates) to process a single 2 Mega Pixel image! This is with the Winograd Transformation; it’s more than 300 Billion without it. And there is a lot of discussion of the large size ... » read more

Embedded FPGA Basics

By Flex Logix - 06 Mar, 2019 - Comments: 0

You do not need know about FPGAs to integrate reconfigurable RTL into your SoC: our software maps your RTL into our EFLX array for you. But if you are curious, read on. FPGAs are field programmable gate arrays. They offer a different kind of programmability from processors. Processors are sequential while FPGAs enable massive parallelism. A processor has one adder, one multiplier—an ... » read more

Edge Inferencing Challenges

By Ed Sperling - 10 Jan, 2019 - Comments: 0

Geoff Tate, CEO of Flex Logix, talks about balancing different variables to improve performance and reduce power at the lowest cost possible in order to do inferencing in edge devices. https://youtu.be/1BTxwew--5U » read more

Looking Beyond The CPU

By Brian Bailey - 29 Nov, 2018 - Comments: 0

CPUs no longer deliver the same kind of of performance improvements as in the past, raising questions across the industry about what comes next. The growth in processing power delivered by a single CPU core began stalling out at the beginning of the decade, when power-related issues such as heat and noise forced processor companies to add more cores rather than pushing up the clock frequency... » read more

Performance Benchmarking Embedded FPGAs

By Flex Logix - 03 Oct, 2018 - Comments: 0

When evaluating the performance of an embedded FPGA, one needs to evaluate the performance of each of the individual modules that make up an FPGA. The basic modules are: Reconfigurable logic building blocks (RBB-Logic), Fine-granularity logic containing LUTs, carry-forwarding adder chain, and flip-flops Reconfigurable DSP building blocks (RBB-DSP), Medium-granularity arith... » read more

Tech Talk: eFPGA Performance Benchmarking

By Ed Sperling - 06 Jun, 2018 - Comments: 0

Tony Kozaczuk, director of system architecture at Flex Logix, explains how to avoid bottlenecks and improve throughput and performance in embedded FPGAs. https://youtu.be/dPDylKG7jhA » read more

Timing Signoff Methodology For eFPGA

By Geoff Tate - 03 May, 2018 - Comments: 0

An eFPGA is a hard IP block in an SoC. Most SoCs are made up of a collection of hard IP blocks (RAM, SerDes, PHYs…) and the remaining logic is constructed using Standard Cells. The timing signoff for an eFPGA’s interface with the rest of the chip is designed to leverage standard ASIC timing signoff flow for a hard-macro: as long as inputs/output to/from the eFPGA are all flopped, the int... » read more

Tech Talk: eFPGA Timing

By Ed Sperling - 03 May, 2018 - Comments: 0

Flex Logix's Chen Wang talks about timing for an embedded FPGA and how that differs from ASIC timing. https://youtu.be/n88D1N4IEbs » read more

Designing 5G Chips

By Ann Mutschler - 18 Apr, 2018 - Comments: 0

5G is the wireless technology of the future, and it’s coming fast. The technology boasts very high-speed data transfer rates, much lower latency than 4G LTE, and the ability to handle significantly higher densities of devices per cell site. In short, it is the best technology for the massive amount of data that will be generated by sensors in cars, IoT devices, and a growing list of next-g... » read more

Tech Talk: On-Chip Variation

By Ed Sperling - 01 Mar, 2018 - Comments: 0

Raymond Nijssen, vice president of systems engineering at Achronix, discusses on-chip and process variation at 7nm and 5nm, the role of embedded FPGAs, and how to reduce margin and pessimistic designs. https://youtu.be/LQnw_3H9soQ » read more

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tag: embedded FPGA

Multi-Layer Processing Boosts Inference Throughput/Watt

Embedded FPGA Basics

Edge Inferencing Challenges

Looking Beyond The CPU

Performance Benchmarking Embedded FPGAs

Tech Talk: eFPGA Performance Benchmarking

Timing Signoff Methodology For eFPGA

Tech Talk: eFPGA Timing

Designing 5G Chips

Tech Talk: On-Chip Variation

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