tag: emulation

Power Limits Of EDA
By Brian Bailey - 13 Oct, 2016 - Comments: 3

Power has become a major gating factor in semiconductor design. It is now the third factor in design optimization, along with performance, and is almost becoming more important than area. But there are limits to the amount of help that [getkc id="7" kc_name="EDA"] can provide with [getkc id="106" kc_name="power optimization"]. Power is not just an optimization problem. It is a design problem... » read more

Deterministic ICE App Tackles ICE Limitations
By Rizwan Farooq - 13 Oct, 2016 - Comments: 0

Historically, SoC verification has used In-Circuit Emulation (ICE) to exercise the design under test (DUT) by connecting physical targets to an emulator. ICE delivers the advantage of being able to run real-world usage scenarios before tape-out. However, an ICE-based verification environment is hampered by several inherent limitations. It is restricted to trigger- and waveform-based debug. W... » read more

Choosing Verification Engines
By Ed Sperling - 05 Oct, 2016 - Comments: 0

Emulation, simulation, FPGA prototyping and formal verification have very specific uses on paper, but the lines are becoming less clear as complexity goes up, more third-party IP is included, and the number of use cases and interactions of connected devices explodes. Ironically, the lines are blurring not for the most complex SoCs, such as those used in smart phones. The bigger challenge app... » read more

Gaps In The Verification Flow
By Brian Bailey - 29 Sep, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss the state of the functional verification flow with Stephen Bailey, director of emerging companies at [getentity id="22017" e_name="Mentor Graphics"]; [getperson id="11079" comment="Anupam Bakshi"], CEO of [getentity id="22168" e_name="Agnisys"]; [getperson id="11124" comment="Mike Bartley"], CEO of [getentity id="22868" e_name="Test and Verification... » read more

Mentor Graphics And IXIA De-Risk Networking SoC Verification
By Mentor, a Siemens Business - 07 Sep, 2016 - Comments: 0

The Veloce VN App bridges the gap between pre-silicon verification and post-silicon validation of networking designs by integrating the industry-leading IXIA virtual networking test solution with the Veloce emulation platform. Networking design teams can now run the same tests in simulation, emulation and the lab. The Veloce VN App supports high performance and offers debug advantage of pre-sil... » read more

Optimization Challenges For 10nm And 7nm
By Brian Bailey - 06 Sep, 2016 - Comments: 0

Optimization used to be a simple timing against area tradeoff but not anymore. As we go to each new node, the tradeoffs become more complicated involving additional aspects of the design that used to be dealt with in isolation. Semiconductor Engineering sat down to discuss these issues with Krishna Balachandran, director of product management for low-power products at [getentity id="22032" e... » read more

Cars, Security, And HW-SW Co-Design
By Jeff Dorsch - 31 Aug, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss parallel hardware/software design with Johannes Stahl, director of product marketing, prototyping and FPGA, [getentity id="22035" e_name="Synopsys"]; [getperson id="11411" comment="Bill Neifert"], director of models technology, [getentity id="22186" comment="ARM"]; Hemant Kumar, director of ASIC design, Nvidia; and Scott Constable, senior member of ... » read more

Context Is Everything
By Ann Mutschler - 29 Aug, 2016 - Comments: 0

With consumer and industrial IoT applications, the importance of system context to IC vendors is paramount. No more are the days of developing a chip in isolation; close partnership with systems companies is de rigueur as they provide the use case data that is foundational to development of systems that work. While this makes sense in a smartphone, it’s significantly harder to achieve in a... » read more

FPGA Prototyping Gains Ground
By Jeff Dorsch - 25 Aug, 2016 - Comments: 0

FPGA technology for design prototypes is making new inroads as demands increase for better integration between hardware and software. [gettech id="31071" comment="FPGA"] prototyping, also known as physical prototyping, has been supported by all of the major EDA players for some time, and it has been considered an essential tool for the largest chipmakers, along with emulation and simulation.... » read more

Optimizing Emulator Utilization
By Russell Klein - 11 Aug, 2016 - Comments: 0

The growing pressures of market schedules, design complexity and the ever-increasing amount of embedded software in today’s SoCs has put verification in the hot-seat. Now that new emulation tools can link hardware and software verification, SoC designers are turning to emulation more than ever before to debug embedded software. The standard method for debugging software with an emulator is wi... » read more

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