tag: emulation

Mentor Graphics And IXIA De-Risk Networking SoC Verification
By Mentor, a Siemens Business - 07 Sep, 2016 - Comments: 0

The Veloce VN App bridges the gap between pre-silicon verification and post-silicon validation of networking designs by integrating the industry-leading IXIA virtual networking test solution with the Veloce emulation platform. Networking design teams can now run the same tests in simulation, emulation and the lab. The Veloce VN App supports high performance and offers debug advantage of pre-sil... » read more

Optimization Challenges For 10nm And 7nm
By Brian Bailey - 06 Sep, 2016 - Comments: 0

Optimization used to be a simple timing against area tradeoff but not anymore. As we go to each new node, the tradeoffs become more complicated involving additional aspects of the design that used to be dealt with in isolation. Semiconductor Engineering sat down to discuss these issues with Krishna Balachandran, director of product management for low-power products at [getentity id="22032" e... » read more

Cars, Security, And HW-SW Co-Design
By Jeff Dorsch - 31 Aug, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss parallel hardware/software design with Johannes Stahl, director of product marketing, prototyping and FPGA, [getentity id="22035" e_name="Synopsys"]; [getperson id="11411" comment="Bill Neifert"], director of models technology, [getentity id="22186" comment="ARM"]; Hemant Kumar, director of ASIC design, Nvidia; and Scott Constable, senior member of ... » read more

Context Is Everything
By Ann Mutschler - 29 Aug, 2016 - Comments: 0

With consumer and industrial IoT applications, the importance of system context to IC vendors is paramount. No more are the days of developing a chip in isolation; close partnership with systems companies is de rigueur as they provide the use case data that is foundational to development of systems that work. While this makes sense in a smartphone, it’s significantly harder to achieve in a... » read more

FPGA Prototyping Gains Ground
By Jeff Dorsch - 25 Aug, 2016 - Comments: 0

FPGA technology for design prototypes is making new inroads as demands increase for better integration between hardware and software. [gettech id="31071" comment="FPGA"] prototyping, also known as physical prototyping, has been supported by all of the major EDA players for some time, and it has been considered an essential tool for the largest chipmakers, along with emulation and simulation.... » read more

Optimizing Emulator Utilization
By Russell Klein - 11 Aug, 2016 - Comments: 0

The growing pressures of market schedules, design complexity and the ever-increasing amount of embedded software in today’s SoCs has put verification in the hot-seat. Now that new emulation tools can link hardware and software verification, SoC designers are turning to emulation more than ever before to debug embedded software. The standard method for debugging software with an emulator is wi... » read more

Optimizing Testbench Acceleration Performance
By Mentor, a Siemens Business - 10 Aug, 2016 - Comments: 0

Part 3 in a series of papers that demystify the performance of SystemVerilog and UVM testbenches when using an emulator for the purpose of hardware-assisted testbench acceleration. In these three papers, architectural and modeling requirements are described, followed by a recommended systematic approach for maximizing overall testbench acceleration speed-up and achieving your ultimate performan... » read more

Time To Pay The Piper
By Brian Bailey - 28 Jul, 2016 - Comments: 3

The Pied Piper of Hamelin is a German fable about a rat catcher who used his magic pipe to lure away rats. When he was not paid by the town, he used his pipe to lure away all of the town's children. I am not suggesting that exactly the same is true for the semiconductor industry and having not paid [getkc id="7" kc_name="EDA"], but I do not think they have paid enough and they will now have to ... » read more

Models Are Dead? Long Live Models
By Frank Schirrmeister - 28 Jul, 2016 - Comments: 0

During the first half of this year I had more discussions with customers on models again. Are models back? For what purpose? In short, it looks like models are well adopted and in use for software development. For performance and architecture analysis, however, as a recent presentation from Renesas at CDNLive Japan shows, users just use RTL as that accuracy is required. In combination with emul... » read more

Making Verification Easier
By Ann Mutschler - 28 Jul, 2016 - Comments: 0

SoC design teams increasingly are confronting complexity in the quest to target application segments, but at the same time they are struggling to more quickly reduce risk in their designs while also speed up testing to make sure everything works. Those often-conflicting goals have transformed [getkc id="10" kc_name="verification"] IP from an interesting concept to a must-have tool for advanc... » read more

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