Balancing Emulation And FPGA-Based Prototyping For Software Development

By Frank Schirrmeister - 30 Jun, 2016 - Comments: 0

This year’s Design Automation Conference (DAC) has just finished and confirmed some of the trends I discussed in my last blog, “The Top Five Trends in Verification to Watch For at DAC 2016”, specifically when it comes to the set of connected engines, or “COVE” as Jim Hogan dubbed it. The Cadence Theater at DAC is always a good opportunity to listen to hands-on customer experiences, an... » read more

Improve DFT Verification And Meet Time-To-Market Goals With Emulation

By Steve Dondershine - 30 Jun, 2016 - Comments: 0

What if all the DFT verification on your next big chip could be completed before tape-out? This “shift-left” of DFT verification would eliminate the need for shortcuts in verification and allow for more types of verification. The benefits of faster and earlier DFT verification include higher confidence in the “golden” RTL, eliminating DFT from the critical path of tape-out, and more pre... » read more

Reducing Design Risk With Testbench Acceleration

By Mentor, a Siemens Business - 29 Jun, 2016 - Comments: 0

Part 1 in a series of papers that demystify the performance of SystemVerilog and UVM testbenches when using an emulator for the purpose of hardware-assisted testbench acceleration. In these three papers, architectural and modeling requirements are described, followed by a recommended systematic approach for maximizing overall testbench acceleration speed-up and achieving your ultimate performan... » read more

Aldec HES Emulation Integration With Imperas OVP

By Aldec - 29 Jun, 2016 - Comments: 0

Virtual platforms play a significant role in system level development, but require the speed that emulation systems provide for hardware/software co-verification. This white paper describes a high performance virtual modeling solution achieved by integrating Aldec’s Transaction Level Emulation System with Imperas’ OVP (Open Virtual Platform) and OVPsim (OVP simulator). Hardware and Software... » read more

System-Level Verification Tackles New Role

By Brian Bailey - 15 Jun, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss advances in system-level verification with Larry Melling, product management director for the system verification group of [getentity id="22032" e_name="Cadence"]; Larry Lapides, vice president of sales for [getentity id="22036" e_name="Imperas”] and Jean-Marie Brunet, director of marketing for the emulation division of [getentity id="22017" e_nam... » read more

System-Level Verification Tackles New Role

By Brian Bailey - 09 Jun, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss advances in system-level verification with Larry Melling, product management director for the system verification group of [getentity id="22032" e_name="Cadence"]; Larry Lapides, VP of sales for [getentity id="22036" e_name="Imperas”] and Jean-Marie Brunet, director of marketing for the emulation division of [getentity id="22017" e_name="Mentor Gr... » read more

DAC Day Three: UVM, Machine Learning And DFT Come Together

By Brian Bailey - 08 Jun, 2016 - Comments: 0

The industry and users have a love/hate relationship with UVM. It has quickly risen to become the most used verification methodology and yet at the same time it is seen as being overly complex, unwieldy and difficult to learn. The third day of DAC gets started with breakfast with Accellera to discuss UVM and what we can expect to see in the next 5 years. The discussion was led by Tom Alsop, pri... » read more

Valtrix Pushes For Horizontal Verification Reuse

By Brian Bailey - 01 Jun, 2016 - Comments: 0

Some of the most significant advances are not the result of a single person or a single idea. They often don’t happen overnight, and are suggested by a change that slowly becomes pervasive enough to become a generalized solution. That is exactly what is happening right now in the area of functional verification. The tools and methodologies in place at the moment assumed designs typical of the... » read more

Formal Confusion

By Brian Bailey - 26 May, 2016 - Comments: 0

Formal verification has come a long way in the past five years. Tool developers changed direction and started to create self-contained apps which have led to a rapid proliferation of the technology. But formal is a diverse set of tools that can solve a variety of problems in the verification space and this has created a different kind of confusion within the industry. To find out how the indust... » read more

Virtual Modeling With Aldec And Imperas

By Aldec - 25 May, 2016 - Comments: 0

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Knowledge Centers
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Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

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tag: emulation

Balancing Emulation And FPGA-Based Prototyping For Software Development

Improve DFT Verification And Meet Time-To-Market Goals With Emulation

Reducing Design Risk With Testbench Acceleration

Aldec HES Emulation Integration With Imperas OVP

System-Level Verification Tackles New Role

System-Level Verification Tackles New Role

DAC Day Three: UVM, Machine Learning And DFT Come Together

Valtrix Pushes For Horizontal Verification Reuse

Formal Confusion

Virtual Modeling With Aldec And Imperas