tag: emulation

System-Level Verification Tackles New Role
By Brian Bailey - 15 Jun, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss advances in system-level verification with Larry Melling, product management director for the system verification group of [getentity id="22032" e_name="Cadence"]; Larry Lapides, vice president of sales for [getentity id="22036" e_name="Imperas”] and Jean-Marie Brunet, director of marketing for the emulation division of [getentity id="22017" e_nam... » read more

System-Level Verification Tackles New Role
By Brian Bailey - 09 Jun, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss advances in system-level verification with Larry Melling, product management director for the system verification group of [getentity id="22032" e_name="Cadence"]; Larry Lapides, VP of sales for [getentity id="22036" e_name="Imperas”] and Jean-Marie Brunet, director of marketing for the emulation division of [getentity id="22017" e_name="Mentor Gr... » read more

DAC Day Three: UVM, Machine Learning And DFT Come Together
By Brian Bailey - 08 Jun, 2016 - Comments: 0

The industry and users have a love/hate relationship with UVM. It has quickly risen to become the most used verification methodology and yet at the same time it is seen as being overly complex, unwieldy and difficult to learn. The third day of DAC gets started with breakfast with Accellera to discuss UVM and what we can expect to see in the next 5 years. The discussion was led by Tom Alsop, pri... » read more

Valtrix Pushes For Horizontal Verification Reuse
By Brian Bailey - 01 Jun, 2016 - Comments: 0

Some of the most significant advances are not the result of a single person or a single idea. They often don’t happen overnight, and are suggested by a change that slowly becomes pervasive enough to become a generalized solution. That is exactly what is happening right now in the area of functional verification. The tools and methodologies in place at the moment assumed designs typical of the... » read more

Formal Confusion
By Brian Bailey - 26 May, 2016 - Comments: 0

Formal verification has come a long way in the past five years. Tool developers changed direction and started to create self-contained apps which have led to a rapid proliferation of the technology. But formal is a diverse set of tools that can solve a variety of problems in the verification space and this has created a different kind of confusion within the industry. To find out how the indust... » read more

Virtual Modeling With Aldec And Imperas
By Aldec - 25 May, 2016 - Comments: 0

Virtual platforms play a significant role in system level development, but require the speed that emulation systems provide for hardware/software co-verification. This white paper describes a high performance virtual modeling solution achieved by integrating Aldec’s Transaction Level Emulation System with Imperas’ OVP (Open Virtual Platform) and OVPsim (OVP simulator). Hardware and Software... » read more

Bringing a Sharper World In Focus With Virtual UHD Verification
By Mentor, a Siemens Business - 11 May, 2016 - Comments: 0

UHD-4K designs require a verification solution that can handle longer, larger frames, faster frame rates, richer colors, wider contrasts, and highly complex chips. Emulation has the speed, capacity, and performance to churn very quickly through the massive amounts of data and long sequences required for verification. Visualization tools are needed to understand and debug what’s going on in UH... » read more

Way Too Much Data
By Ed Sperling - 28 Apr, 2016 - Comments: 0

Moving to the next process nodes will produce volumes more data, forcing chipmakers to adopt more expensive hardware to process and utilize that data, more end-to-end methodologies, as well as using tools and approaches that in the past were frequently considered optional. Moreover, where that data needs to be dealt with is changing as companies adopt a "shift left" approach to developing so... » read more

Bridging Hardware And Software
By Ann Mutschler - 28 Apr, 2016 - Comments: 1

The barriers between hardware and software design and verification are breaking down with more intricately integrated systems, bringing together different disciplines and tools. But there are lingering questions about exactly what this shift means design methodologies, team interactions, and what kind of training will be required in the future. Playing heavily into this is the fact that toda... » read more

System-Level Verification Tackles New Role
By Brian Bailey - 28 Apr, 2016 - Comments: 0

Wally Rhines, chairman and CEO of Mentor Graphics, gave the keynote at DVCon this year. He said that if you pull together a bunch of pre-verified IP blocks, it does not change the verification problem at the system level. That sounds like a problem. There are assumptions made that the IP blocks work to a reasonable degree, and that when performing system-level verification the focus is not a... » read more

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