tag: emulation

Stories From The Village Called Hardware-Assisted Development
By Frank Schirrmeister - 28 Apr, 2016 - Comments: 0

They say it takes a village to raise children and, as a dad of an 11-year-old girl, I can relate. Similarly, for system development and hardware-assisted verification, the overall ecosystem of users, use models, and partners is equally important. The recent CDNLive Silicon Valley event is a great example. The SoC and Hardware/Software track that my team and I were hosting featured NVIDIA, Netro... » read more

Are Simulation’s Days Numbered?
By Brian Bailey - 26 Apr, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss the limitations of simulation in more complex designs with [getperson id="11049" comment="Michael McNamara"], CEO of [getentity id="22716" comment="Adapt-IP”]; Pete Hardee, product management director at [getentity id="22032" e_name="Cadence"]; David Kelf, vice president of marketing for for [getentity id="22395" e_name="OneSpin Solutions"]; Lauro... » read more

The Week In Review: Design/IoT
By Jesse Allen - 15 Apr, 2016 - Comments: 0

Mergers & Acquisitions Cadence acquired [getentity id="22444" comment="Rocketick"], an Israel-based company focused on multicore parallel simulation. Founded in 2008, their original rise and claim to fame was acceleration on GPUs, having received significant funding from Nvidia. The deal is expected to close in the second quarter of fiscal 2016, and terms were not disclosed. Tools &am... » read more

Are Simulation’s Days Numbered?
By Brian Bailey - 06 Apr, 2016 - Comments: 3

Semiconductor Engineering sat down to discuss the limitations of simulation in more complex designs with [getperson id="11049" comment="Michael McNamara"], CEO of [getentity id="22716" comment="Adapt-IP”]; Pete Hardee, product management director at [getentity id="22032" e_name="Cadence"]; David Kelf, vice president of marketing for [getentity id="22395" e_name="OneSpin Solutions"]; Lauro Riz... » read more

A Formal Transformation
By Brian Bailey - 24 Mar, 2016 - Comments: 0

A very important change is underway in functional verification. In the past, this was an esoteric technology and one that was difficult to deploy. It was relegated to tough problems late in the verification cycle, and it was difficult to justify the ROI unless the technology actually did find some problems. But all of that has changed. Formal verification companies started to use the technology... » read more

An Unsustainable Divide
By Brian Bailey - 24 Mar, 2016 - Comments: 0

One of the great things about attending DVCon, or any other conference for that matter, is the networking. You get to see so many people who are eager to learn, to talk and to share ideas. When this happens, you tend to hear a lot of statements that have to rattle around in your mind for a while before you can start to make sense of them and see if any coherent themes emerge. By themes, I am... » read more

Are Simulation’s Days Numbered?
By Brian Bailey - 24 Mar, 2016 - Comments: 0

In the latest EDAC report, the value of IP surpassed the value of CAE tools for the first time. Verification tools are an important part of establishing confidence in IP blocks and simulation has been the mainstay of that IP verification strategy. But simulation is under increasing pressure, particularly for full-chip and SoC verification, because it has failed to scale. While it still remains ... » read more

Accelerating Design-For-Test Pattern Simulation
By Mentor, a Siemens Business - 23 Mar, 2016 - Comments: 0

The Veloce DFT App presents a true “left shift” improvement for a traditional chip design schedule that requires comprehensive gate-level simulations to develop ATPG, BIST, or functional patterns. It enables running complete patterns for DFT verification in a reasonable time to shorten the pattern development cycle. The Veloce DFT App fits seamlessly into the Veloce ecosystem, enabling a ho... » read more

Power Analysis Plus Power Management
By Ellie Burns - 10 Mar, 2016 - Comments: 0

In my earlier blogs we've heard from some of the experts on using UPF in the successive refinement flow. We’ve talked about controlling leakage power, bringing power down, and validating power management behavior using coverage and simulation, including debug and clock domain crossing verification. In order to do the last step in the successive refinement flow, you need to use emulation be... » read more

Power — Usage Shift Leads to Methodology Shift
By Mentor, a Siemens Business - 09 Mar, 2016 - Comments: 0

Power exploration and accurate power calculation of SoCs in the target application environment is getting executive attention due to the fact that companies are missing market windows because of power issues. This makes system-level power analysis and management a key measurement. Verification solutions that provide accurate power analysis data early are critical to making design decisions that... » read more

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