New Product Introduction Process For Heterogeneous 2.5D Devices

By Javier DeLaCruz - 28 Mar, 2014 - Comments: 0

For the past few years, the most popular topics in the 2.5D space have been: The design tools Foundry processes for through-silicon vias, temporary bonding and bump architecture The assembly process, such as what is first bonded to what The industry is at the point where the open variables on these topics are narrowing, and other critical aspects need to get far better attention. The... » read more

Self-Service Semiconductors

By Mike Gianfagna - 27 Mar, 2014 - Comments: 1

The era of self-service is here. Whether you’re in a restaurant, shopping center, airport or cruising the Web, you have more options than ever to browse, research, choose and transact business with little to no human interaction. Self-service isn’t a new concept. In fact, it’s been around a long time. What is new is the pervasive use of high-tech automation to deliver experiences t... » read more

Evolution Vs. Revolution

By Ann Mutschler - 27 Feb, 2014 - Comments: 1

In the electronic design automation industry changes to tools and flows are nearly always evolutionary. They hide as much change from the user as possible, allowing easier justification from an ROI perspective, and they raise far fewer objections from users, who don’t have to spend time learning how to use new technology or rethink tried and true approaches to problems. Revolution in chip ... » read more

Abstractions: The Good, Bad And Ugly

By Ed Sperling - 27 Feb, 2014 - Comments: 0

Raising the level of abstraction has become almost a mantra among chipmakers and tools developers. By moving the vantage point up a couple rungs on the ladder, it’s easier to see how the individual parts of a design go together, to identify problems in the design as well as fixes to problems, and it all can happen much more quickly. That’s the theory, at least. And in most cases, it’s ... » read more

Week In Review: System-Level Design

By Ed Sperling - 07 Feb, 2014 - Comments: 0

Cadence agreed to buy Forte Design Systems for an undisclosed sum, adding further proof that the market for high-level synthesis and tools that run at higher levels of abstraction is finally hitting its stride. Behind this acquisition is a rising pain level due to increasing complexity in SoCs—IP integration, low power concerns and much more of everything, from transistors to memories—has f... » read more

Blog Review: Feb. 5

By Ed Sperling - 05 Feb, 2014 - Comments: 0

Mentor’s J. VanDomelen notes that the Mars colonization selection process has begun, with the actual colonization scheduled to begin in 2025. Remember to bring your own air, water, food, a sewing kit, and lots of reading material. You also may need leg weights for bone density maintenance. What happens if you build a processor using memory as the starting point? Cadence’s Richard Goerin... » read more

The Growing Verification Challenge

By Ed Sperling - 30 Jan, 2014 - Comments: 1

As complexity continues to mount in designing SoCs, so does the challenge of verifying them within the same time window and using the same compute and engineering resources. Chipmakers aren’t always successful at this. In many cases they have to put more engineers on the verification and debug at the tail end of a design to get it out the door on or close to schedule. In many cases that al... » read more

Ticket to Ride

By Mike Gianfagna - 30 Jan, 2014 - Comments: 0

Welcome to the newly named eSilicon blog. We’ll discuss topics of general interest related to the semiconductor industry here. Our blog title does however take us off the hook to have complete, rational and defensible points of view at all times. Let’s begin… Do you like a roller coaster ride? Some do and some, well, get sick at the thought. I’m here to tell you that if you’re invo... » read more

Experts At The Table: Yield And Reliability Issues With Integrating IP

By Ed Sperling - 27 Jan, 2014 - Comments: 1

Semiconductor Engineering sat down to discuss the impact of integrating IP in complex SoCs with Juan Rey, senior director of engineering at Mentor Graphics; Kevin Yee, product marketing director for Cadence’s SoC Realization Group; and Mike Gianfagna, vice president of marketing at eSilicon. What follows are excerpts of that conversation. SE: As an industry we’ve got a pretty good grasp ... » read more

The Road Ahead for 2014: Semiconductors

By Brian Bailey - 23 Jan, 2014 - Comments: 1

Last week, Semiconductor Engineering examined the 2014 predictions from several thought leaders in the industry and published those predictions that related to general market trends. Many of those predictions require some advances in semiconductor technologies and fabrications capabilities. It is those predictions that will be examined in this part, followed next week by the predictions related... » read more

← Older posts Newer posts →

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.