tag: eSilicon

Will It Really Work?
By Ed Sperling - 26 Jan, 2012 - Comments: 0

By Ed Sperling Estimates of how much time it takes to verify a complex SoC are still hovering around 70% of the total non-recurring engineering costs, but with more unknowns and more things to verify it’s becoming harder to keep that number from growing. Verification has always been described as an unbounded problem. You can always verify more, and just knowing when to call it quits is so... » read more

Rebalancing Power, Performance And Area
By Ed Sperling - 15 Dec, 2011 - Comments: 0

By Ed Sperling The tradeoffs between performance, power and area are being fine-tuned to a degree never seen before in the IC business, driven partly by complexity, partly by better tools, and partly by the need to gain a competitive edge in specific applications. Just being able to make these kinds of tradeoffs is a technological feat that marries everything from high-level modeling and sy... » read more

Experts At The Table: Stacked Die And The Supply Chain
By Ed Sperling - 13 Dec, 2011 - Comments: 0

By Ed Sperling Semiconductor Manufacturing & Design sat down to discuss the effects of stacking die on the supply chain with Stephen Pateras, production marketing director for silicon test at Mentor Graphics; Javier DeLaCruz, director of manufacturing technology at eSilicon; Colin Baldwin, director of marketing at Open-Silicon; Charles Woychik, director of marketing and technical analysis ... » read more

Experts At The Table: Stacked Die And The Supply Chain
By Ed Sperling - 05 Dec, 2011 - Comments: 0

By Ed Sperling Semiconductor Manufacturing & Design sat down to discuss the effects of stacking die on the supply chain with Stephen Pateras, production marketing director for silicon test at Mentor Graphics; Javier DeLaCruz, director of manufacturing technology at eSilicon; Colin Baldwin, director of marketing at Open-Silicon; Charles Woychik, director of marketing and technical analysis ... » read more

Experts At The Table: Stacked Die And The Supply Chain
By Ed Sperling - 26 Nov, 2011 - Comments: 0

By Ed Sperling Semiconductor Manufacturing & Design sat down to discuss the effects of stacking die on the supply chain with Stephen Pateras, production marketing director for silicon test at Mentor Graphics; Javier DeLaCruz, director of manufacturing technology at eSilicon; Colin Baldwin, director of marketing at Open-Silicon; Charles Woychik, director of marketing and technical analysis... » read more

Make Vs. Buy
By Ed Sperling - 17 Nov, 2011 - Comments: 0

By Ann Steffora Mutschler The confounding ‘make versus buy’ decision is understandably muddled by design complexity. Millions of gates, thousands of blocks, dozens of cores, plus software, packaging, and worries about physical effects don’t make this decision any easier. In some cases the process can be simplified by mandating that anything that doesn’t add differentiation really is... » read more

The Next SoCs
By Ed Sperling - 20 Oct, 2011 - Comments: 0

By Ed Sperling The number of changes that will hit the IC market over the next few years is almost staggering by any standard—past or present. In addition to the relentless pressure of Moore’s Law, there will be new materials, new structures, and new models for developing and packaging chips. System-Level Design asked executives from across the SoC ecosystem what will change, what’s d... » read more

Derivative Designs Demand Discipline
By Ed Sperling - 20 Oct, 2011 - Comments: 0

By Ann Steffora Mutschler By and large most designs today are derivatives, meaning they don’t start from a blank slate. And while that gives engineering teams a starting point, it also can make adding new IP blocks or changes to the design problematic, with the potential for increased routing and timing issues along with considerable pain to back-end engineers and delays in chip schedules. ... » read more

VIP: Behind The Velvet Rope
By Ed Sperling - 20 Oct, 2011 - Comments: 0

By Ann Steffora Mutschler Some years ago, as engineering teams began to incorporate more protocols into designs and as those protocols grew in sophistication and complexity in order to deliver additional performance, the verification task grew concurrently. At the same time, the design IP market was growing as complexity drove re-use of components, along with verification components—most com... » read more

Solid Verification Methodology Essential To Productivity
By Ann Mutschler - 22 Sep, 2011 - Comments: 0

Verifying SoCs from a functional perspective pushes the limits of already lean resources, driving verification teams to seek out new ways to improve productivity of verification tasks. Of course, with the verification task being a time-bound one, the challenge is daunting. It is well understood that consumer electronics is pushing the technology envelope in terms of the amount of technology ... » read more

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