Debug Tops Verification Tasks

By Ann Mutschler - 20 Dec, 2018 - Comments: 0

Verification engineers are spending an increased percentage of their time in debug — 44%, according to a recent survey by the Wilson Research Group. There are a variety or reasons for this, including the fact that some SoCs are composed of hundreds of internally developed and externally purchased IP blocks and subsystems. New system architectures contribute to the mix, some of which are be... » read more

What Makes A Chip Design Successful Today?

By Brian Bailey - 13 Dec, 2018 - Comments: 0

"Transistors are free" was the rallying cry of the semiconductor industry during the 1990s and early 2000s. That is no longer true. The end of Dennard scaling made the simultaneous use of all the transistors troublesome, but transistors remained effectively unlimited. This led to an era where large amounts of flexibility could be built into a chip. It didn't matter if all of it was being use... » read more

Where Advanced Packaging Makes Sense

By Ed Sperling - 10 Dec, 2018 - Comments: 0

Semiconductor Engineering sat down with Chenglin Liu, director of package engineering at Marvell; John Hunt, senior director of engineering at ASE; Eric Tosaya, senior director of package manufacturing at eSilicon; and Juan Rey, vice president of engineering for Calibre at Mentor, a Siemens Business. What follows are excerpts of that discussion, which was held in front of a live audience at MEP... » read more

Making Sure A Heterogeneous Design Will Work

By Ed Sperling - 03 Dec, 2018 - Comments: 0

An explosion of various types of processors and localized memories on a chip or in a package is making it much more difficult to verify and test these devices, and to sign off with confidence. In addition to timing and clock domain crossing issues, which are becoming much more difficult to deal with in complex chips, some of the new devices are including AI, machine learning or deep learning... » read more

Supercomputers Are For Everyone

By Mike Gianfagna - 29 Nov, 2018 - Comments: 0

Our SerDes world tour continues. This past month, we demonstrated our 7nm 56G long-reach SerDes in Dallas and Israel. In Dallas, our demonstration included error-free operation in 56G PAM4 over a 30dB channel without forward error correction through an eye-popping five-meter cable. Many thanks to our partner Samtec for providing that cable, allowing backplane designers to now “reach beyond th... » read more

Why 56Gb/s And 112Gb/s SerDes Matter In Our Daily Social-Media-Driven Lives

By eSilicon - 28 Nov, 2018 - Comments: 0

Hyper-scalers and service providers are moving from 100GbE to 400GbE Ethernet rates and beyond. Wireline and wireless networks are driving new architectures to support the move from 4G LTE to 5G infrastructure. These transitions are driven by the increasing global IP traffic as the world becomes more connected and digital. At the same time, the decentralization of the cloud and data centers are... » read more

Some Chipmakers Sidestep Scaling, Others Hedge

By Ed Sperling - 15 Nov, 2018 - Comments: 0

The rising cost of developing chips at 7nm coupled with the reduced benefits of scaling have pried open the floodgates for a variety of options involving new materials, architectures and packaging that either were ignored or not fully developed in the past. Some of these approaches are closely tied to new markets, such as assisted and autonomous vehicles, robotics and 5G. Others involve new ... » read more

AI Begins To Reshape Chip Design

By Ed Sperling - 01 Nov, 2018 - Comments: 1

Artificial intelligence is beginning to impact semiconductor design as architects begin leveraging its capabilities to improve performance and reduce power, setting the stage for a number of foundational shifts in how chips are developed, manufactured and updated in the future. AI—and machine learning and deep learning subsets—can be used to greatly improve the functional control and pow... » read more

Week In Review: Design, Low Power

By Jesse Allen - 26 Oct, 2018 - Comments: 0

Tools OneSpin launched a formal verification tool that integrates with all major simulators, coverage databases and viewers, and chip design verification planning tools to provide a comprehensive view of verification progress. Comprised of two new formal apps, it can identify unreachable coverage points and provide them to the simulator to reduce wasted effort. Synopsys released the latest ... » read more

EDA Cloud Adoption Hits Speed Bumps

By Brian Bailey - 25 Oct, 2018 - Comments: 0

If moving semiconductor design to the Cloud was easy and beneficial, everyone would be doing it. But so far, few have done more than dip a toe. The level of difficulty associated with migrating to the Cloud varies, depending upon who you talk to. The reality is that not everyone makes it as easy as it could be, or is not willing to put the necessary effort into making it easier. There is cer... » read more

← Older posts Newer posts →

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: eSilicon