tag: etch

Novel Etch Technologies Utilizing Atomic Layer Process For Advanced Patterning
By TEL - 17 Dec, 2020 - Comments: 0

We demonstrated a high selective and anisotropic plasma etch of Si3N4 and SiC. The demonstrated process consists of a sequence of ion modification and chemical dry removal steps. The Si3N4 etch with H ion modification showed a high selectivity to SiO2 and SiC films. In addition, we have developed selective etch of SiC with N ion modification. On the other hand, in the patterning etch processes,... » read more

Accelerating Dry Etch Processes During Feature Dependent Etch
By Timothy Yang - 23 Nov, 2020 - Comments: 0

In dry etching, the trajectory of accelerated ions is non-uniform and non-vertical, due to collisions with gas molecules and other random thermal effects (figure 1). This has an impact on etch results, since the etch rate at any point on the wafer will vary depending on the solid angle visible to the bulk chamber and the ion flux for that angular range. These non-uniform and feature dependent e... » read more

Upturn Seen In Semi Equipment Biz
By Mark LaPedus - 17 Sep, 2020 - Comments: 0

Business continues to get better in the semiconductor equipment sector. VLSI Research, for one, has raised its forecast in the arena. But there is still some uncertainty amid mixed growth for semiconductors, trade wars and other factors. After a downturn in 2019, the semiconductor equipment market expected an upturn in 2020. Then, the Covid-19 pandemic struck. Suddenly, a large percentage... » read more

Making Chips At 3nm And Beyond
By Mark LaPedus and Ed Sperling - 16 Apr, 2020 - Comments: 4

Select foundries are beginning to ramp up their new 5nm processes with 3nm in R&D. The big question is what comes after that. Work is well underway for the 2nm node and beyond, but there are numerous challenges as well as some uncertainty on the horizon. There already are signs that the foundries have pushed out their 3nm production schedules by a few months due to various technical issu... » read more

An Introduction To Semiconductor Process Modeling
By Jeonghoon (James) Kim - 20 Dec, 2019 - Comments: 0

Semiconductor process engineers would love to develop successful process recipes without the guesswork of repeated wafer testing. Unfortunately, developing a successful process can’t be done without some work. This blog will discuss an efficient technique to develop new process steps faster, with much less effort. Basic concept The easiest way to predict a process result is to model its b... » read more

Cloudy Outlook Seen For IC Biz
By Mark LaPedus - 29 Jul, 2019 - Comments: 0

After a slowdown in the first half of 2019, chipmakers and equipment vendors face a cloudy outlook for the second half of this year, with a possible recovery in 2020. Generally, the semiconductor industry began to see a slowdown starting in mid- to late-2018, which extended into the first half of 2019. During the first half of this year, memory and non-memory vendors were negatively impacted... » read more

200mm Cools Off, But Not For Long
By Mark LaPedus - 18 Jul, 2019 - Comments: 4

After years of acute shortages, 200mm fab capacity is finally loosening up, but the supply/demand picture could soon change with several challenges on the horizon. 200mm fabs are older facilities with more mature processes, although they still churn out a multitude of today’s critical chips, such as analog, MEMS, RF and others. From 2016 to 2018, booming demand for these and other chips ca... » read more

Single Vs. Multi-Patterning EUV
By Mark LaPedus - 25 Mar, 2019 - Comments: 5

Extreme ultraviolet (EUV) lithography finally is moving into production, but foundry customers now must decide whether to implement their designs using EUV-based single patterning at 7nm, or whether to wait and instead deploy EUV multiple patterning at 5nm. Each patterning scheme has unique challenges, making that decision more difficult than it might appear. Targeted for 7nm, single pattern... » read more

Unsticking Moore’s Law
By Ed Sperling - 04 Feb, 2019 - Comments: 2

Sanjay Natarajan, corporate vice president at Applied Materials with responsibility for transistor, interconnect and memory solutions, sat down with Semiconductor Engineering to talk about variation, Moore's Law, the impact of new materials such as cobalt, and different memory architectures and approaches. What follows are excerpts of that conversation. SE: Reliability is becoming more of an... » read more

Planarization Challenges At 7nm And Beyond
By Ed Sperling - 10 Dec, 2018 - Comments: 0

Dan Sullivan, executive director of semiconductor technology at Brewer Science, digs into the challenges of planarizing a thin film on a wafer for etch and optical control. The problem becomes more difficult at advanced nodes because the films are thinner. https://youtu.be/iNA6EGpoYZU     _________________________________ See more tech talk videos here   » read more

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