tag: ETH Zurich

Memory Wall Problem Grows With LLMs
By Katherine Derbyshire - 20 Feb, 2025 - Comments: 0

The growing imbalance between the amount of data that needs to be processed to train large language models (LLMs) and the inability to move that data back and forth fast enough between memories and processors has set off a massive global search for a better and more energy- and cost-efficient solution. Much of this is evident in the numbers. The GPU market is forecast to reach $190 billion in ... » read more

Temporal Variation in DRAM Read Disturbance in DDR4 and HBM2 (ETH Zurich, Rutgers)
By Technical Paper Link - 19 Feb, 2025 - Comments: 0

A new technical paper titled "Variable Read Disturbance: An Experimental Analysis of Temporal Variation in DRAM Read Disturbance" was published by researchers at ETH Zurich and Rutgers University. Abstract "Modern DRAM chips are subject to read disturbance errors. State-of-the-art read disturbance mitigations rely on accurate and exhaustive characterization of the read disturbance threshold... » read more

Chip Industry Technical Paper Roundup: Feb. 10
By Linda Christensen - 10 Feb, 2025 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=405 /] Find all technical papers here. Also find more research and latest news here. » read more

Optimization of the Inter-Chiplet Interconnect And The Chiplet Placement (ETH Zurich, U. of Bologna)
By Technical Paper Link - 04 Feb, 2025 - Comments: 0

A new technical paper titled "PlaceIT: Placement-based Inter-Chiplet Interconnect Topologies" was published by researchers at ETH Zurich and University of Bologna. Abstract "2.5D integration technology is gaining traction as it copes with the exponentially growing design cost of modern integrated circuits. A crucial part of a 2.5D stacked chip is a low-latency and high-throughput inter-ch... » read more

Chip Industry Technical Paper Roundup: Feb. 4
By Linda Christensen - 04 Feb, 2025 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=403 /] Find all technical papers here. » read more

Processing-Using-DRAM: Attaining High-Performance Via Dynamic Precision Bit-Serial Arithmetic (ETH Zurich, et al.)
By Technical Paper Link - 01 Feb, 2025 - Comments: 0

A new technical paper titled "Proteus: Achieving High-Performance Processing-Using-DRAM via Dynamic Precision Bit-Serial Arithmetic" was published by researchers at ETH Zurich, Cambridge University, Universidad de Córdoba, Univ. of Illinois Urbana-Champaign and NVIDIA Research. Abstract "Processing-using-DRAM (PUD) is a paradigm where the analog operational properties of DRAM structures ... » read more

Chip Industry Technical Paper Roundup: Jan. 7
By Linda Christensen - 07 Jan, 2025 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=395 /] Find all technical papers here. » read more

Recent Advances and Challenges in Processing-in-DRAM (ETH Zurich)
By Technical Paper Link - 30 Dec, 2024 - Comments: 0

A new technical paper titled "Memory-Centric Computing: Recent Advances in Processing-in-DRAM" was published by researchers at ETH Zurich. Abstract "Memory-centric computing aims to enable computation capability in and near all places where data is generated and stored. As such, it can greatly reduce the large negative performance and energy impact of data access and data movement, by 1) ... » read more

Chip Industry Technical Paper Roundup: Dec. 3
By Linda Christensen - 03 Dec, 2024 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=391 /] » read more

Backpropagation Algorithm On Neuromorphic Spiking HW (U. Of Zurich, ETH Zurich, LANL)
By Technical Paper Link - 25 Nov, 2024 - Comments: 0

A new technical paper titled "The backpropagation algorithm implemented on spiking neuromorphic hardware" was published by University of Zurich, ETH Zurich, Los Alamos National Laboratory, Royal Institution, London, et al. "This study presents a neuromorphic, spiking backpropagation algorithm based on synfire-gated dynamical information coordination and processing implemented on Intel’s Lo... » read more

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