Chip Industry Week In Review


By Jesse Allen, Karen Heyman, and Liz Allan AMD took the covers off new AI accelerators for training and inferencing of large language model and high-performance computing workloads. In its announcement, AMD focused heavily on performance leadership in the commercial AI processor space through a combination of architectural changes, better software efficiency, along with some improvements in... » read more

Chip Industry’s Technical Paper Roundup: Dec 5


New technical papers recently added to Semiconductor Engineering’s library: [table id=171 /] More ReadingTechnical Paper Library home » read more

Alleviating the DRAM Capacity Bottleneck in Consumer Devices with NVMs


A new technical paper titled "Extending Memory Capacity in Modern Consumer Systems With Emerging Non-Volatile Memory: Experimental Analysis and Characterization Using the Intel Optane SSD" was published by researchers at ETH Zurich, University of Illinois Urbana-Champaign, Google, and Rivos. Abstract Excerpt "DRAM scalability is becoming a limiting factor to the available memory capacity in... » read more

Technical Paper Roundup: November 28


New technical papers recently added to Semiconductor Engineering’s library: [table id=169 /] More Reading Technical Paper Library home » read more

A Fast And Unified Toolchain For Rapid Design Space Exploration Of Chiplet Architectures


A technical paper titled “RapidChiplet: A Toolchain for Rapid Design Space Exploration of Chiplet Architectures” was published by researchers at ETH Zurich and University of Bologna. Abstract: "Chiplet architectures are a promising paradigm to overcome the scaling challenges of monolithic chips. Chiplets offer heterogeneity, modularity, and cost-effectiveness. The design space of chiplet ... » read more

Fast Interrupt Extension For MCU RISC-V


A technical paper titled “CV32RT: Enabling Fast Interrupt and Context Switching for RISC-V Microcontrollers” was published by researchers at ETH Zurich and University of Bologna. Abstract: "Processors using the open RISC-V ISA are finding increasing adoption in the embedded world. Many embedded use cases have real-time constraints and require flexible, predictable, and fast reactive handl... » read more

Chip Industry’s Technical Paper Roundup: November 6


New technical papers added to Semiconductor Engineering’s library this week. [table id=162 /] More Reading Technical Paper Library home » read more

A Modelling Approach To Well-Known And Exotic 2D Materials For Next-Gen FETs


A technical paper titled “Field-Effect Transistors based on 2-D Materials: a Modeling Perspective” was published by researchers at ETH Zurich. Abstract: "Two-dimensional (2D) materials are particularly attractive to build the channel of next-generation field-effect transistors (FETs) with gate lengths below 10-15 nm. Because the 2D technology has not yet reached the same level of maturity... » read more

CPU Fuzzing Via Intricate Program Generation (ETH Zurich)


A technical paper titled “Cascade: CPU Fuzzing via Intricate Program Generation” was published by researchers at ETH Zurich. Abstract: "Generating interesting test cases for CPU fuzzing is akin to generating programs that exercise unusual states inside the CPU. The performance of CPU fuzzing is heavily influenced by the quality of these programs and by the overhead of bug detection. Our a... » read more

Chip Industry’s Technical Paper Roundup: October 17


New technical papers added to Semiconductor Engineering’s library this week. [table id=155 /] More Reading Technical Paper Library home » read more

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