SRAM efficiency and performance; channel-last GAA NS oxide transistors; DL model for nanomaterials; HW acceleration for neural networks; memristive FeRAM; scalable AI/ML method for MTJs; HBM for AI inference; HW fuzzing; MoS2 memristors with fast switching for low power.
New technical papers recently added to Semiconductor Engineering’s library:
| Technical Paper | Research Organizations |
|---|---|
| Prefill vs. Decode Bottlenecks: SRAM-Frequency Tradeoffs and the Memory-Bandwidth Ceiling | Uppsala University |
| Channel-last gate-all-around nanosheet oxide semiconductor transistors | Stanford, TSMC, ETH Zurich, SLAC, Polish Academy of Sciences |
| Deep-learning atomistic semi-empirical pseudopotential model for nanomaterials | UC Berkeley, LBNL, Brown University et al. |
| Hardware Acceleration for Neural Networks: A Comprehensive Survey | Arizona State University |
| Nitride Ferroelectric Domain Wall Memory for Next-Generation Computing | Kiel University, Fraunhofer ISIT, NaMLab, TU Dresden |
| LEAD: Literature Enhanced Ab Initio Discovery of Nitride Dusting Layers for Enhanced Tunnel Magnetoresistance and Lower Resistance Magnetic Tunnel Junctions | UT Austin, TSMC, TDK Headway |
| Making Strong Error-Correcting Codes Work Effectively for HBM in AI Inference | Rensselaer Polytechnic Institute, ScaleFlux, IBM T.J. Watson Research Center |
| GoldenFuzz: Generative Golden Reference Hardware Fuzzing | TU Darmstadt |
| Intermediate Resistive State in Wafer-Scale Vertical MoS2 Memristors Through Lateral Silver Filament Growth for Artificial Synapse Applications | AMO GmbH, RWTH Aachen, Forschungszentrum Jülich, Peter Grünberg Institute, TU Eindhoven et al. |
Find more semiconductor research papers here.
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