Chip Industry’s Technical Paper Roundup: October 17


New technical papers added to Semiconductor Engineering’s library this week. [table id=155 /] More Reading Technical Paper Library home » read more

Chip Industry Talent Shortage Drives Academic Partnerships


Universities around the world are forming partnerships with semiconductor companies and governments to help fill open and future positions, to keep curricula current and relevant, and to update and expand skills for working engineers. Talent shortages repeatedly have been cited as the number one challenge for the chip industry. Behind those concerns are several key drivers, and many more dom... » read more

Patterning With EUV Lithography Without Photoresists


A technical paper titled “Resistless EUV lithography: photon-induced oxide patterning on silicon” was published by researchers at Paul Scherrer Institute, University College London, ETH Zürich, and EPFL. Abstract: "In this work, we show the feasibility of extreme ultraviolet (EUV) patterning on an HF-treated Si(100) surface in the absence of a photoresist. EUV lithography is the leading ... » read more

Chip Industry’s Technical Paper Roundup: Sept 19


New technical papers added to Semiconductor Engineering’s library this week. [table id=141 /] More Reading Technical Paper Library home » read more

A Hierarchical Instruction Cache Tailored To Ultra-Low-Power Tightly-Coupled Processor Clusters


A technical paper titled “Scalable Hierarchical Instruction Cache for Ultra-Low-Power Processors Clusters” was published by researchers at University of Bologna, ETH Zurich, and GreenWaves Technologies. Abstract: "High Performance and Energy Efficiency are critical requirements for Internet of Things (IoT) end-nodes. Exploiting tightly-coupled clusters of programmable processors (CMPs) ha... » read more

Chip Industry Week In Review


By Gregory Haley, Jesse Allen, and Liz Allan TSMC told equipment vendors to delay deliveries of the most advanced tools due to uncertain demand, according to Reuters. The news drove down stock prices of all the major equipment providers. On the other hand, TSMC said advanced packaging shortages will constrain AI chip shipments for the next 18 months, according to NikkeiAsia. The United St... » read more

DRAM Simulator For Evaluation of Memory System Design Changes (ETH Zurich)


A technical paper titled “Ramulator 2.0: A Modern, Modular, and Extensible DRAM Simulator” was published by researchers at ETH Zurich. Abstract: "We present Ramulator 2.0, a highly modular and extensible DRAM simulator that enables rapid and agile implementation and evaluation of design changes in the memory controller and DRAM to meet the increasing research effort in improving the perfo... » read more

Technical Paper Roundup: Sept 5


New technical papers added to Semiconductor Engineering’s library this week. [table id=132 /] (more…) » read more

Security Research: Technical Paper Round-up


A number of hardware security-related technical papers were presented at the August 2023 USENIX Security Symposium. Here are some highlights with associated links. [table id=130 /] A complete listing of all papers presented at this summer's USENIX conference can be found here and here. The organization provides open access research, and the presentation slides and papers are free to the p... » read more

Contacting Individual On-Surface Synthesized Graphene Nanoribbons In A Multigate Transistor Geometry 


A technical paper titled “Contacting individual graphene nanoribbons using carbon nanotube electrodes” was published by researchers at Swiss Federal Laboratories for Materials Science and Technology, Peking University, University of Warwick, National Center for Nanoscience and Technology (China), Max Planck Institute for Polymer Research, University of Bern, University of Basel, and ETH Zur... » read more

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