The History Of CMOS


Since CMOS has been around for about 50 years, a comprehensive history would be a book. This blog focuses on what I consider the major transitions. NMOS Before CMOS, there was NMOS (also PMOS, but I have no direct experience with that). An NMOS gate consisted of a network of N-transistors between the output and Vss, and a resistor (actually a transistor with an implant) between the output and... » read more

Assist Layers: The Unsung Heroes of EUV Lithography


Most discussions of advanced lithography focus on three elements — the exposure system, photomasks, and photoresists — but that's only part of the challenge. Successfully transferring a pattern from the photomask to a physical structure on the wafer also depends on a variety of films working together, including the underlayers, the developers, and a variety of surface treatments. In fact... » read more

Nanoimprint Finally Finds Its Footing


Nanoimprint lithography, which for decades has trailed behind traditional optical lithography, is emerging as the technology of choice for the rapidly growing photonics and biotech chips markets. First introduced in the mid-1990s, nanoimprint lithography (NIL) has consistently been touted as a lower-cost alternative to traditional optical lithography. Even today, NIL potentially is capable o... » read more

Large-Scale Nanometer-Thick Graphite Film (NGF) As A EUV Pellicle


A new technical paper titled "Graphite Pellicle: Physical Shield for Next-Generation EUV Lithography Technology" was published by researchers at University of Ottawa, Sungkyunkwan University, and Hanbat National University. Abstract "Extreme ultraviolet lithography (EUVL) is widely employed in the electronics, automotive, military, and AI computing areas for IC chip fabrication. A pellicl... » read more

Tech Forecast: Fab Processes To Watch Through 2040


The massive proliferation of semiconductors in more markets, and more applications within those markets, is expected to propel the industry to more than $1 trillion by 2030. But over the next 17 years, semiconductors will reach well beyond the numbers, changing the way people work, how they communicate, and how they measure and monitor their health and well-being. Chips will be the enabling ... » read more

Evolution Of The EUV Ecosystem Reflected At 2023 Advanced Lithography + Patterning


As anticipated, this year’s Advanced Lithography + Patterning Symposium was a very informative event, with many interesting papers being presented across a wide range of subjects. Many papers addressed topics relevant to leading-edge lithography, which these days means EUV lithography. With EUV lithography firmly established in high volume manufacturing (HVM), we could see in the presentation... » read more

Metrology Strategies For 2nm Processes


Metrology and wafer inspection processes are changing to keep up with evolving and new device applications. While fab floors still have plenty of OCD tools, ellipsometers, and CD-SEMs, new systems are taking on the increasingly 3D nature of structures and the new materials they incorporate. For instance, processes like hybrid bonding, 3D NAND flash devices, and nanosheet FETs are pushing the bo... » read more

Process Innovations Enabling Next-Gen SoCs and Memories


Achieving improvements in performance in advanced SoCs and packages — those used in mobile applications, data centers, and AI — will require complex and potentially costly changes in architectures, materials, and core manufacturing processes. Among the options under consideration are new compute architectures, different materials, including thinner barrier layers and those with higher th... » read more

Devices And Transistors For The Next 75 Years


The 75th anniversary of the invention of the transistor sparked a lively panel discussion at IEDM, spurring debate about the future of CMOS, the role of III-V and 2D materials in future transistors, and what will be the next great memory architecture.[1] Industry veterans from the memory, logic, and research communities see high-NA EUV production, NAND flash with 1,000 layers, and hybrid bon... » read more

Screening For Silent Data Errors


Engineers are beginning to understand the causes of silent data errors (SDEs) and the data center failures they cause, both of which can be reduced by increasing test coverage and boosting inspection on critical layers. Silent data errors are so named because if engineers don’t look for them, then they don’t know they exist. Unlike other kinds of faulty behaviors, these errors also can c... » read more

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