tag: EUV

Ivy Bridge Settles Old Bet
By Marc David Levenson - 16 Aug, 2012 - Comments: 0

Think back seven years to 2005. Those were boom times with the housing market rising, the dollar high, 65nm node chips on the horizon and EUV the great future lithography hope. EUVL was late for the next (45nm) node, but a great new idea had appeared to fill the gap—water immersion scanning with 193nm exposure! But how far could wet 193nm lithography go before EUVL or some new thing, such as ... » read more

Double Patterning: Challenges And Possible Solutions In Parasitics Extraction
By David Abercrombie - 16 Aug, 2012 - Comments: 0

By Dusan Petranovic and David Abercrombie Double patterning (DP), as the simplest form of multi-patterning techniques, is receiving lots of attention right now. The need for double patterning techniques is driven by the physical limits of the dimensions that can be resolved with current light sources and lenses, as well as by the difficulties and delays in deploying next-generation lithography... » read more

Litho Community Meets And Votes
By Marc David Levenson - 31 Jul, 2012 - Comments: 0

Every 18 months or so, the leading lithography lights of the IEEE meet in an off-the-record workshop to discuss the state and future of our craft. This year’s event took place amid the restored colonial splendor of Williamsburg Virginia in June. Co-chairs Mordechai Rothschild and Lars Liebmann assembled a technical program that covered not only lithography for semiconductor manufacturing, but... » read more

DSA Moves To R&D Pilot Lines
By Ed Sperling - 31 Jul, 2012 - Comments: 0

By Mark LaPedus Directed self-assembly (DSA), an alternative lithography technology that makes use of block copolymers, is still in the R&D stage for semiconductor production. But as the exotic patterning technology continues to make astounding progress, there are signs the IC industry is accelerating its efforts to bring DSA from the lab to the fab. In fact, DSA suddenly has become a ... » read more

Investment Options
By Ed Sperling - 31 Jul, 2012 - Comments: 0

It's clear that something fundamental has changed in the semiconductor manufacturing industry. What's less clear is how this will play out over the long term. Intel's agreement to invest more than $4 billion in ASML to ensure the continued development of EUV and 450mm wafer technology is more than just a one-off deal. It's a very public recognition that the astronomical cost of design and ma... » read more

More Design Rules Ahead
By Ed Sperling - 25 Jul, 2012 - Comments: 0

By Ed Sperling & Mark LaPedus For those companies that continue to push the limits of feature shrinkage, designs are about to become more difficult, far more expensive—and much more regulated. Two converging factors will force these changes. First, the limits of current 193nm immersion lithography mean companies now must double pattern at 20nm, and potentially quadruple pattern at 14n... » read more

Experts At The Table: Multipatterning
By Ed Sperling - 20 Jul, 2012 - Comments: 0

By Ed Sperling Semiconductor Manufacturing & Design sat down with Michael White, physical verification product line manager at Mentor Graphics; Luigi Capodieci, R&D fellow at GlobalFoundries; Lars Liebmann, IBM distinguished engineer; Rob Aitken, ARM fellow; Jean-Pierre Geronimi, CAD director at STMicroelectronics; and Kuang-Kuo Lin, director of foundry design enablement at Samsung Ele... » read more

Future Foundry Issues
By Ed Sperling - 13 Jul, 2012 - Comments: 0

Semiconductor Manufacturing & Design talks with Luigi Capodieci, fellow at GlobalFoundries, about EUV, the challenges at 20nm and beyond, and the future of the foundry model. [youtube vid=YXov4y0kpfU] » read more

Four Factors Driving Processor Choices
By Ed Sperling - 12 Jul, 2012 - Comments: 0

By Ed Sperling Choosing processors for an SoC, a system-in-package, or even a complete system is becoming much more difficult, and the challenge is growing as demands on performance, power, area and time to market continue to increase. There are many reasons why this is becoming more difficult—and some designs will require more tradeoffs than others, depending upon IP re-use or a particul... » read more

All Indicators Point North
By Ed Sperling - 28 Jun, 2012 - Comments: 0

Designing and producing chips has always been difficult, but the number of things that conspire to make it harder at 20nm is the longest in the history of the semiconductor industry. The list will grow longer still at 14nm and beyond, not to mention so expensive that one mistake will kill a company. While system engineers and architects look at the challenges on the front end, the problems ... » read more

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