Potentials And Issues Of Designing Fault-Tolerant Hardware Acceleration For Edge-Computing Devices

A technical paper titled “Fault-Tolerant Hardware Acceleration for High-Performance Edge-Computing Nodes” was published by researchers at University of Rome. Abstract: "High-performance embedded systems with powerful processors, specialized hardware accelerators, and advanced software techniques are all key technologies driving the growth of the IoT. By combining hardware and software tec... » read more

Why It’s So Difficult To Ensure System Safety Over Time

Safety is emerging as a concern across an increasing number of industries, but standards and methodologies are not in place to ensure electronic systems attain a defined level of safety over time. Much of this falls on the shoulders of the chip industry, which provides the underlying technology, and it raises questions about what more can be done to improve safety. A crude taxonomy recently ... » read more

Overview of Machine Learning Algorithms Used In Hardware Security (TU Delft)

A new technical paper titled "A Survey on Machine Learning in Hardware Security" was published by researchers at TU Delft. Abstract "Hardware security is currently a very influential domain, where each year countless works are published concerning attacks against hardware and countermeasures. A significant number of them use machine learning, which is proven to be very effective in ... » read more

Mitigating Silent Data Corruptions in High Performance Computing

A new technical paper titled "Mitigating silent data corruptions in HPC applications across multiple program inputs" was published by researchers at University of Iowa, Baidu Security, and Argonne National Lab. The paper was a Best Paper finalist at SC22. The researchers "propose MinpSID, an automated SID framework that automatically identifies and re-prioritizes incubative instructions in a... » read more

Glitched On Earth By Humans

The Black Hat conference always brings up interesting and current research within the device security industry. Lennert Wouters of COSIC studied the security of the Starlink User Terminal. After some PCB-level reverse engineering, he found a serial port and observed various boot loaders, U-boot, and Linux running on the device. However, there was no obvious way to gain further access. The... » read more

Functional Safety Verification Of Serial Peripheral Interface

A new technical paper titled "FMEDA based Fault Injection to Validate Safety Architecture of SPI" was published by researchers at R.V. College of Engineering in India and Analog Devices. Abstract "The integration of advanced technologies into Electrical Vehicles (EV) has been increasing in recent times, so it has become crucial to evaluate the risk of the technologies that are deployed into... » read more

Secure Physical Design Roadmap Enabling End-To-End Trustworthy IC Design Flow

The FICS Research Institute (University of Florida) has published a new research paper titled "Secure Physical Design." This is the first and most comprehensive research work done in this area that requires significant attention from academia, industry, and government for ensuring trust in electronic design automation flow," said lead author Sukanta Dey. Abstract "An integrated circuit is s... » read more

Building Security Into ICs From The Ground Up

Cyberattacks are becoming more frequent and more sophisticated, but they also are starting to compromise platforms that until recently were considered unbreakable. Consider blockchains, for example, which were developed as secure, distributed ledger platforms. All of them must be updated with the same data for a transaction to proceed. But earlier this year a blockchain bridge platform calle... » read more

A Novel ISO 26262-Compliant Test Bench to Assess the Diagnostic Coverage of Software Hardening Techniques against Digital Components Random Hardware Failures

Abstract "This paper describes a novel approach to assess detection mechanisms and their diagnostic coverage, implemented using embedded software, designed to identify random hardware failures affecting digital components. In the literature, many proposals adopting fault injection methods are available, with most of them focusing on transient faults and not considering the functional safety st... » read more

Hardware Countermeasures Benchmarking against Fault Attacks

Abstract "The development of differential fault analysis (DFA) techniques and mechanisms to inject faults into cryptographic circuits brings with it the need to use protection mechanisms that guarantee the expected level of security. The AES cipher, as a standard, has been the target of numerous DFA techniques, where its security has been compromised through different formulations and types of... » read more

← Older posts