tag: FD-SOI

One PHY Does Not Fit All
By Rita Horner - 14 May, 2015 - Comments: 0

Consumers expect their battery-operated mobile devices to be faster, smaller and more reliable while providing greater functionality at a reduced cost. Most of all, consumers demand longer battery life and 24/7 access to data. To meet these demands, consumer system-on-a-chip (SoC) designers must make tradeoffs between features, performance, power and cost. Enterprise SoC designers have their... » read more

FD-SOI Vs. FinFETs
By Ed Sperling - 13 May, 2015 - Comments: 3

Semiconductor Engineering sat down to compare the benefits, risks and challenges of moving to finFETs compared with fully depleted silicon on insulator ([getkc id="220" kc_name="FD-SOI"]) with Philippe Magarshack, group vice president for technology R&D at [getentity id="22331" comment="STMicroelectronics"]; Marco Brambilla, director of engineering at [getentity id="22150" e_name="Synapse D... » read more

FD-SOI Vs. FinFETs
By Ed Sperling - 30 Apr, 2015 - Comments: 0

Semiconductor Engineering sat down to compare the benefits, risks and challenges of moving to finFETs compared with fully depleted silicon on insulator ([getkc id="220" kc_name="FD-SOI"]) with Philippe Magarshack, group vice president for technology R&D at [getentity id="22331" comment="STMicroelectronics"]; Marco Brambilla, director of engineering at [getentity id="22150" e_name="Synapse D... » read more

What EDA’s Big 3 Think Now
By Ed Sperling - 23 Apr, 2015 - Comments: 0

In the past two months the CEOs of Cadence, Synopsys and Mentor Graphics delivered their annual high-level messages to their respective user groups. Semiconductor Engineering attended all of the speeches at these conferences, as it did in 2014 (see story here). From a high level, the big issues for CEOs last year were Moore's Law, the costs of design, the impact of low power, and business-... » read more

FD-SOI Vs. FinFETs
By Ed Sperling - 16 Apr, 2015 - Comments: 1

Semiconductor Engineering sat down to compare the benefits, risks and challenges of moving to finFETs compared with fully depleted silicon on insulator ([getkc id="220" kc_name="FD-SOI"]) with Philippe Magarshack, group vice president for technology R&D at [getentity id="22331" comment="STMicroelectronics"]; Marco Brambilla, director of engineering at [getentity id="22150" e_name="Synapse D... » read more

TSMC Tech Tour De Force
By Barry Pangrle - 13 Apr, 2015 - Comments: 0

TSMC held the first of its three North American Tech Symposiums on April 7 in San Jose, with the other two coming up in Boston on April 14 and in Austin on April 16. As was mentioned previously here, the record fast ramp-time of the 20nm node was highlighted among other technological achievements. TSMC also released its March revenue report on April 10, and it shows a dramatic 49.8% increase in... » read more

Will Wearables Work Well Enough?
By Ed Sperling - 02 Apr, 2015 - Comments: 0

By Ed Sperling & Ann Steffora Mutschler The rollout of the Apple Watch later this month has reset expectations for the wearable electronics market, just as early implementations of the Pebble, Fitbit and Google Glass helped raise awareness about a new level of portability and connectivity. Early projections are for strong sales, which in turn will propel a new level of connectedness for the ... » read more

FD-SOI Meets The IoT
By Ann Mutschler - 05 Feb, 2015 - Comments: 1

Silicon-on-insulator manufacturing technology has been discussed for many years. IBM has used the partially depleted variation of SOI in its server products, but the fully depleted version has yet to find widespread adoption outside of mil/aero and automotive markets. That may change soon as applications in the Internet of Things ramp, given the requirements for ultra low power and low cost.... » read more

One-On-One: Aaron Thean
By Mark LaPedus - 22 Jan, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss process technology, transistor trends and other topics with Aaron Thean, vice president of process technologies and director of the logic devices R&D program at Imec. SE: Chipmakers are ramping up the 16nm/14nm logic node, with 10nm and 7nm in R&D. What’s the current timeline for 10nm and 7nm? Thean: 10nm is on its way. We will see r... » read more

Trouble Spots And Optimism For 2015
By Ed Sperling - 18 Dec, 2014 - Comments: 0

Most top executives in the semiconductor industry are bullish about 2015 and even beyond, particularly as the [getkc id="76" comment="Internet of Things"] begins to drive new markets and market mash-ups, and as more semiconductors find their way into markets such as automotive, health-care and manufacturing. But it's not an entirely rosy picture, and top executives point to potential trouble sp... » read more

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