FD-SOI Meets The IoT

A number of silicon-on-insulator process variations have been discussed and implemented for years. Will the fully depleted variant find widespread use in the IoT.


Silicon-on-insulator manufacturing technology has been discussed for many years. IBM has used the partially depleted variation of SOI in its server products, but the fully depleted version has yet to find widespread adoption outside of mil/aero and automotive markets.

That may change soon as applications in the Internet of Things ramp, given the requirements for ultra low power and low cost. Alternatively, the technology could remain a niche process for mil/aero and automotive.

What is interesting about FD-SOI versus other options is that, especially at the 28nm node, a fully depleted transistor is used, explained Giorgio Cesana, director of technology marketing at STMicroelectronics. “When we compare 28nm FD-SOI with the 16/14nm node, it has the advantage to be still a single-patterning node with a cost dimension that is kept well under control. This is absolutely important because IoT is not just the wearables where you can sell a watch at $200. The high volumes will be on products that are maybe sold at $10, $5 — even $1.”

Many of these parts will require a low cost and fully integrated solution. “FD-SOI, implementing fully depleted transistors in a planar technology, is allowing a simpler and easier way to co-integrate multiple functionalities. Of course we can have the digital, we can have the analog and mixed-signal, we have an RF option on the FD-SOI so we can do RF co-integrated in the same SoC,” Cesana noted.

There is also an ultra-low voltage capability, which means that thanks to the fact that the transistor is fully depleted, the transistors can operate at very low voltage. “This is essential for IoT applications that get their energy maybe from harvesting vibrations, solar or whatever. It’s absolutely important to be able to operate at the lowest possible power consumption,” he explained.

Drew Wingard, CTO of Sonics, pointed out that published transistor-level results for FD-SOI are very attractive. “With the cost tradeoff to get a certain level of performance and leakage power, FD-SOI looks cheaper than finFETs, but obviously they are swimming upstream against a huge amount of momentum that’s focused on trying to make finFETs cheap. The real question is can the FD-SOI people build a strong enough ecosystem in time before they are basically overwhelmed by Moore’s Law?”

Wingard noted there is a reasonable belief and a reasonable amount of funding that’s coming from EU sources, and that ST has signed up Samsung as a second source for the technology. “They are doing the right steps to make this ecosystem happen, but the reality of the world is that without a sufficient quantity of hard IP to handle all the different kinds of PHY interfaces, this technology doesn’t look like a safe bet for fabless chip companies. They’ve got a chicken and egg problem. They’ve got to fund the development of all of that without enough customers, and the customers won’t show up without it. They are trying to break through the chicken and egg.”

ST’s Cesana noted this is exactly what the company had in mind when it decided to make its FD-SOI set available. “We have solved the problem of foundry. The ecosystem will continue to build up and spread if there is an IP offer. We said if we wait, Synopsys or Cadence or whomever will develop IP. Of course, there is a chicken and egg problem because they will start developing only when they see customers. And of course customers will start thinking about FD-SOI when they will see IPs. Internally, we have developed plenty of IP. We took those IP and made them available to the market through a reseller/IP vendor. They have integrated the IPs that are silicon-proven, as those IPs are also used in ST products and in ST customer’s products, and they have made those IPs as their own.”

He cites increasing interest in co-integration of analog and digital functionality as FD-SOI works extremely well there. “For example, in analog since the transistor is fully depleted, it has a much better analog gain, it has a better mismatch, so all of the figures of merit that are of interest for an analog design are extremely good. Maybe designing a complex SoC where you integrate multiple functionalities, adding analog, maybe also adding RF takes more time that’s true because validating analog IP takes more time, but it has a huge advantage in the end because of power consumption. When you go on different, for example, a front end module which is containing the RF and the backend module which is containing the digital, for the time to market it’s nice because you can reuse things that you already have in house, but then from a power consumption point of view, the solution is not at all optimal because you have two chips to communicate together. When you co-integrate and have everything on the SoC, of course, you are on a form factor which is much more effective because the die is smaller, packaging is simpler and so on. Also, in terms of power, you are much more efficient.”

(The SOI Industry Consortium hosted an FD-SOI and RF-SOI Forum in Tokyo on Jan. 23. There is another forum planned for the end of this month in San Francisco. http://www.soiconsortium.org/fully-depleted-soi/presentations/january-2015/)

Fuzzy timeline
So when will FD-SOI see widespread adoption? “FD-SOI on 28nm has been available since 2013 but has not seen a major company or product adopt the technology,” noted Joanne Itow, managing director of manufacturing at Semico Research. “In May 2014, STM and Samsung announced a partnership to offer FD-SOI. That provided a second source for capacity and the expectation that a major product announcement might occur before the end of 2014. There is still no announcement of any major product or application moving to FD-SOI. And as time passes, a significant amount of R&D has occurred for finFETs and the learning curve will reduce the cost of 16/14nm finFET.”

Semico expects IBM will most likely continue to utilize SOI, which means eventually it will move to FD-SOI on 28nm and possibly 14nm, and Big Blue will continue to target its process and ASIC products in servers and communication infrastructure products.

“There is a possibility that Sony could move back to SOI at the 14nm node for gaming processors,” Itow said. “Nintendo continues to use SOI. There is also the possibility of IoT products utilizing FD-SOI in lieu of moving to 20nm/14nm in order to avoid double patterning and keep costs down. However, as time passes, the cost of 20nm capacity and bulk 28nm continues to fall, which reduces the cost/benefit of FD-SOI for IoT products,” Itow added.

But don’t count FD-SOI out just yet. While the most advanced, high-volume or price-insensitive chips will always push to the next node, there is a whole layer of companies and applications that don’t warrant the added steps of double patterning, triple patterning, or vertical transistor design. And FD-SOI can be used as one component in a stacked die configuration, where the extra patterning steps are not required.

Marco Brambilla, director of engineering at Synapse Design, stressed that FD-SOI is happening now and the industry leaders are ready. “Synapse Design has taped out four designs and has chosen FD-SOI for a new ultra-low-power device being designed now and will tape out soon. STMicroelectronics design kits are stable. The fact that Samsung has decided to license the technology is also a great opportunity, because it automatically allows high-volume devices the possibility of a second source.”

Further, he said, Synapse is in discussions with several customers that are starting work on FD-SOI designs, both at ST and Samsung. These customers are spanning the spectrum from high-volume consumer devices all the way to low-volume, complex and big chips. “The tide will rise once Samsung announces production maturity.”

Brambilla sees mostly a power benefit — obtained without sacrificing speed. “In the chip we’re developing, we’re seeing better speed at 28nm FD-SOI 0.8V than in 40LP at 1.1V at a fraction of the power. He said one of Synapse’s customers has completed an analysis at each FD-SOI node, and found the power/performance is better than one smaller node in FD-SOI. “This is most likely peculiar to their own application, but it provides us with an idea that the technology is well suited for power reduction. We have also seen the technology used on large ASICs, for products needing 24/7 operation in data centers. In this case again the choice was dictated by the fact that the same performances were reached with a significantly lower power footprint.”

Huzefa Cutlerywala, senior director for technical solutions at Open-Silicon, asserted that the cost of doing chips at advanced nodes is becoming too high, which prompted the company to look into FD-SOI. “Until [about three years ago] FD-SOI was seen as a niche technology, very expensive yet had value from a power and performance perspective. But more recently some of the fabs have been able to show it’s really not that expensive. While the bare wafer is expensive, converting that wafer into an FD-SOI wafer is not expensive. And more recently, there have been more companies that come up that manufacture SOI wafers now. The technology definitely addresses the power problem quite nicely because it reduces leakage quite dramatically compared to bulk CMOS.”

He concedes there has been talk about design challenges but stressed that Open-Silicon has worked closely with an FD-SOI fab over the last two years on the libraries, IP and have gone through a complete design process to make sure that as they bring this out to customers there are no issues.

Open-Silicon has engaged with a customer on a test chip, which should be taping out soon, Cutlerywala added.

But even given technical readiness, is there a scenario in which FD-SOI is a niche process option, or will it be the ideal process technology for IoT apps?

Mitch Lowe, vice president of research and development at Cadence, said there is certainly customer interest, but he hasn’t seen any big movements. “If there was a splash, some marquis that could point to somebody who was not doing this before and decided to shift and was successful at it, that would make a difference. Short of that, I don’t see a whole lot of interest.”

Arvind Narayanan, product marketing manager for the Place & Route Division at Mentor Graphics, agreed that customers are seeing the power and performance advantage of FD-SOI without having to scale to smaller technology node. But they are still not adopting it en masse.

Still, could it end up being a niche for mil/aero? ”It’s quite possible, the reason being when we look at mobile devices/smartphone market segment, some of these customers have already started designing at 20/16/14 finFETs. If that gains enough momentum then they don’t look back and say they have to pay a little bit more for moving to finFET but are getting the best possible performance and area savings. The tools are ready, so that very well may be the chase. But it’s too early to tell. Tier 1 smartphone customers (like Apple or Samsung) already are using FinFETs, so now it’s a questions of Tier 2 and what their option will be and how it’s going to pan out.”

Kevin Kranen, director of strategic alliances at Synopsys, noted the company has done a number of different SOI-related project over the past decade, has worked with various vendors, and has put together a complete design flow.

“It’s one of those things where there’s still one more layer to be chipped at before you see rapid adoption,” Kranen said. “Then the question really becomes how many more nodes do we have. I do hear a lot of end customer interest — a little bit of it is tire kicking — but a lot of it is they are trying to figure out if this is a better cost solution, a lower-risk solution than jumping into some of the advanced node technologies.”


Ian Dedic says:

The hidden advantage of FDSOI over FinFET for very low-power (or dynamic power dominated) applications is that in the end the power to perform an operation is CV^2, and minimum Vdd is limited by how low you can set Vth to keep leakage under control in the fast process corner (and high temperature) and still have the circuit function in the slow process corner (and low temperature). With FDSOI the Vth variation can be tuned out using the back gate, which allows Vdd to be >100mV lower than FinFET where this is not possible. Added to the the fact that C is higher for FinFET (more parasitics), this gives a big power advantage to FDSOI for very low voltage low power operation.

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