tag: finFET

Hot Stuff
By Ann Mutschler - 14 Mar, 2013 - Comments: 0

By Ann Steffora Mutschler When it comes to thermal modeling, which has been practiced for many years, the challenges are daunting. The good news is that approaches are emerging as challenges increased with smaller process nodes and design complexity. Viewed from a number of viewpoints—transistor, chip, package, board and system—thermal models traditionally have been created from m... » read more

Good Pattern Flow Ahead For 14, 10nm
By Ann Mutschler - 21 Feb, 2013 - Comments: 0

By Ann Steffora Mutschler Given complexity, yield, power and other challenges with leading edge manufacturing, semiconductor foundries increasingly have been forced to require more and more restrictive design rules with each new process node. “They keep adding more design rules and more operations to a particular check to eliminate corner cases where in manufacturing they saw some variant... » read more

Foundry Arms Race Under Way
By Mark LaPedus - 21 Feb, 2013 - Comments: 0

By Mark LaPedus A year ago, chipmakers were reeling from a severe shortage of 28nm foundry capacity, prompting foundries to ramp up their fabs at a staggering pace. At the time, foundries were unable to keep up with huge and unforeseen demand for mobile chips. The shortfall was also caused by low yields and the overall lack of installed 28nm capacity. Today, the 28nm crunch is largely ov... » read more

SOI Highlights at Common Platform Tech Forum
By Various Writers - 19 Feb, 2013 - Comments: 0

Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News ~  ~ The 2013 Common Platform Technology Forum showcased “the latest technological advances being delivered to the world’s leading electronics companies,” so of course SOI-based topics were well-represented. Happily, those of us who weren’t able to get over to Silicon Valley were able to attend “virtually” via a ... » read more

Good Times For Analog Designers
By Ann Mutschler - 14 Feb, 2013 - Comments: 1

By Ann Steffora Mutschler For a number of technological reasons, analog/mixed-signal design and low-power design are converging, and with that comes both challenges and opportunities. As far as challenges go, process variations at 14nm, 20nm and even 28nm have increased significantly to include DFM impacts such as layout-delay effects. On the digital side, those process changes affect... » read more

ST-Ericsson 28nm FD-SOI/ARM Chip Hits 2.8GHz at CES
By Various Writers - 22 Jan, 2013 - Comments: 0

Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News ~  ~ What a great start to 2013: at CES in Las Vegas, ST-Ericsson announced the NovaThor™ L8580 ModAp, “the world’s fastest and lowest-power integrated LTE smartphone platform.” This is the one that’s on STMicroelectronics’ 28nm FD-SOI, with sampling set for Q1 2013. And it’s a game changer – for users, fo... » read more

Mix-And-Match Power Options
By Ed Sperling - 06 Dec, 2012 - Comments: 0

By Ann Steffora Mutschler Choices abound today when it comes to considering a node shrink. Fully depleted silicon on insulator (FD-SOI) and finFET technologies along with other advanced transistor options are being evaluated, both together and independently of the other. It is possible to implement finFET on bulk 28nm CMOS or finFET on an FD-SOI process, for example. It is also possible to imp... » read more

Chip Architect Challenges
By Ed Sperling - 06 Dec, 2012 - Comments: 0

By Ann Steffora Mutschler Product lifecycles can be shorter than the design cycle and even the process development cycle, particularly in the consumer handheld device market. It’s up to the chip architect to decide how the functions should be implemented. The good news is there are a number of options available, ranging from mapping the design to 2.5D technology, moving to finFET tr... » read more

Experts At The Table: Obstacles In Low-Power Design
By Ed Sperling - 06 Dec, 2012 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss low-power design with with Leah Clark, associate technical director at Broadcom; Richard Trihy, director of design enablement at GlobalFoundries; Venki Venkatesh, engineering director at Atrenta; and Qi Wang, technical marketing group director at Cadence. What follows are excerpts of that conversation. LPHP: If you ar... » read more

Experts At The Table: Obstacles In Low-Power Design
By Ed Sperling - 06 Dec, 2012 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss low-power design with with Leah Clark, associate technical director at Broadcom; Richard Trihy, director of design enablement at GlobalFoundries; Venki Venkatesh, engineering director at Atrenta; and Qi Wang, technical marketing group director at Cadence. What follows are excerpts of that conversation. LPHP: If you ar... » read more

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