A Deposition And Etch Technique To Lower Resistance Of Semiconductor Metal Lines

By Timothy Yang - 20 Apr, 2023 - Comments: 0

Copper's resistivity depends on its crystal structure, void volume, grain boundaries and material interface mismatch, which becomes more significant at smaller scales. The formation of copper (Cu) wires is traditionally done by etching a trench pattern in low-k silicon dioxide using a trench etch process, and subsequently filling the trench with Cu via a damascene flow. Unfortunately, this meth... » read more

IEDM: TSMC N3 Details

By Paul McLellan - 26 Jan, 2023 - Comments: 0

I attended IEDM in San Francisco in December. There were two presentations about TSMC's N3 process. This is actually a bit of a misnomer since TSMC has two N3 processes, one simply called N3. The other (the second generation) is called N3E. The two papers were: Critical Process Features Enabling Aggressive Contacted Gate Pitch Scaling for 3nm CMOS Technology and Beyond A 3nm CMOS FinFl... » read more

Automatic Layout Generator Targeting Region-based Layouts for Advanced FinFET-Based Full-Custom Circuits (UT Austin/NVIDIA)

By Technical Paper Link - 15 Dec, 2022 - Comments: 0

A technical paper titled "AutoCRAFT: Layout Automation for Custom Circuits in Advanced FinFET Technologies" was published by researchers at UT Austin and NVIDIA. "This paper presents AutoCRAFT, an automatic layout generator targeting region-based layouts for advanced FinFET-based full-custom circuits. AutoCRAFT uses specialized place-and-route (P&R) algorithms to handle various design cons... » read more

Novel Multi-Independent Gate-Controlled FinFET Technology

By Technical Paper Link - 08 Nov, 2022 - Comments: 0

A new technical paper titled "Characteristics of a Novel FinFET with Multi-Enhanced Operation Gates (MEOG FinFET)" was published by researchers at Changzhou University. Abstract: "This study illustrates a type of novel device. Integrating fin field-effect transistors (FinFETs) with current silicon-on-insulator (SOI) wafers provides an excellent platform to fabricate advanced specific device... » read more

L-FinFET Neuron For A Highly Scalable Capacitive Neural Network (KAIST)

By Technical Paper Link - 31 Oct, 2022 - Comments: 0

A new technical paper titled "An Artificial Neuron with a Leaky Fin-Shaped Field-Effect Transistor for a Highly Scalable Capacitive Neural Network" was published by researchers at KAIST (Korea Advanced Institute of Science and Technology). “In commercialized flash memory, tunnelling oxide prevents the trapped charges from escaping for better memory ability. In our proposed FinFET neuron, t... » read more

Cryogenic CMOS Becomes Cool

By Brian Bailey - 11 Aug, 2022 - Comments: 1

Cryogenic CMOS is a technology on the cusp, promising higher performance and lower power with no change in fabrication technology. The question now is whether it becomes viable and mainstream. Technologies often appear to be just on the horizon, not quite making it, but never too far out of sight. That's usually because some issue plagues it, and the incentive is not big enough to solve the ... » read more

Chipmaking In The Third Dimension

By Krishnan Shrinivasan - 16 Jun, 2022 - Comments: 0

Every few months, new and improved electronics are introduced. They’re typically smaller, smarter, faster, have more bandwidth, are more power-efficient, etc. — all thanks to a new generation of advanced chips and processors. Our digital society has come to expect this steady drip of new devices as sure as the sun will rise tomorrow. Behind the scenes, however, engineers are working feve... » read more

Emulation-Centric Power Analysis Of SoC Designs

By Lauro Rizzatti - 09 Jun, 2022 - Comments: 0

Verification expert Lauro Rizzatti recently interviewed Jean-Marie Brunet, senior marketing director, Scalable Verification Solutions Division (SVSD), Siemens EDA, about the importance of accurate power estimation and optimization for system-on-chip (SoC) designs. What is the problem facing the semiconductor industry today regarding pre-silicon power estimation? The problem is the discrep... » read more

End In Sight For Chip Shortages?

By Mark LaPedus - 18 Nov, 2021 - Comments: 2

The current wave of semiconductor and IC packaging shortages is expected to extend well into 2022, but there are also signs that supply may finally catch up with demand. The same is true for manufacturing capacity, materials and equipment in both the semiconductor and packaging sectors. Nonetheless, after a period of shortages in all segments, the current school of thought is that chip suppl... » read more

Four-Period Vertically Stacked SiGe/Si Channel FinFET Fabrication and Its Electrical Characteristics

By Technical Paper Link - 28 Aug, 2021 - Comments: 0

Li Y, Zhao F, Cheng X, Liu H, Zan Y, Li J, Zhang Q, Wu Z, Luo J, Wang W. Four-Period Vertically Stacked SiGe/Si Channel FinFET Fabrication and Its Electrical Characteristics. Nanomaterials (Basel). 2021 Jun 28;11(7):1689. doi: 10.3390/nano11071689. PMID: 34203194; PMCID: PMC8307669. Find technical paper here. Abstract "In this paper, to solve the epitaxial thickness limit and the high in... » read more

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tag: finFET

A Deposition And Etch Technique To Lower Resistance Of Semiconductor Metal Lines

IEDM: TSMC N3 Details

Automatic Layout Generator Targeting Region-based Layouts for Advanced FinFET-Based Full-Custom Circuits (UT Austin/NVIDIA)

Novel Multi-Independent Gate-Controlled FinFET Technology

L-FinFET Neuron For A Highly Scalable Capacitive Neural Network (KAIST)

Cryogenic CMOS Becomes Cool

Chipmaking In The Third Dimension

Emulation-Centric Power Analysis Of SoC Designs

End In Sight For Chip Shortages?

Four-Period Vertically Stacked SiGe/Si Channel FinFET Fabrication and Its Electrical Characteristics

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