tag: finFET

The Week In Review: Manufacturing
By Mark LaPedus - 21 Nov, 2014 - Comments: 0

A majority of Americans cannot endure more than two hours without checking their electronic devices, according to new data released in the Crucial.com Tech-Life Balance Survey. One in four Americans becomes stressed by going longer than 30 minutes without checking their email or phone due to a fear of missing out. Additionally, one in five would sooner go to dinner with an ex significant other ... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 17 Oct, 2014 - Comments: 0

It’s official: IBM appears to be exiting the chip business. After months of talks, IBM has agreed to pay GlobalFoundries $1.5 billion to take Big Blue’s chip unit off its hands, according to reports from Bloomberg. IBM will also receive $200 million worth of assets, according to the reports. At the upcoming IEEE International Electron Devices Meeting (IEDM), Intel and IBM will present... » read more

Time To Look At SOI Again
By Mark LaPedus - 16 Oct, 2014 - Comments: 0

Chipmakers have the luxury of looking at several process options when developing chips at the 28nm node and beyond. Using bulk CMOS, for example, chipmakers can scale planar transistors down to 20nm. Then, at 20nm, planar runs out of gas due to the so-called short-channel effect. At that point, IC makers must migrate towards finFETs at 16nm/14nm and beyond. Another process option is fully... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 03 Jul, 2014 - Comments: 0

Looking to address a new wave of chip architectures in the marketplace, Applied Materials has rolled out its next-generation, medium-current ion implanter. The system, dubbed the VIISta 900 3D, is geared for the production of finFETs and 3D NAND designs at the sub-2xnm nodes. Typically, medium-current implanters have a maximum energy range of about 900keV (triple-charge), with dose ranges fr... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 20 Jun, 2014 - Comments: 0

According to one analyst, the capital spending picture looks gloomy. “We expect finFET and 3D NAND to ramp over the next two years. However, foundry and memory customers are showing great restraint with respect to spending plans, limiting the rate of new node transitions and overall capex upside. In the near term, we see no evidence of meaningful equipment orders to support high-volume finFET... » read more

Has The IC Industry Hit A ‘Red Brick Wall’?
By Mark LaPedus - 19 Jun, 2014 - Comments: 2

In the mid-1980s, the semiconductor industry was in a crisis. Chipmakers were looking for ways to break the magical one-micron barrier. Many thought X-ray lithography would be required to break the barrier, but as it turned out, traditional optical technology did the trick. And the industry marched on. Then, in 2000 or so, the IC industry was nearing the so-called “red brick wall,” which... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 25 Apr, 2014 - Comments: 0

Worldwide semiconductor capital equipment spending is projected to total $37.5 billion in 2014, an increase of 12.2% from 2013 spending of $33.5 billion, according to Gartner. Capital spending will increase 5.5% in 2014 as the industry begins to recover from the recent economic downturn. The 3D NAND market will take longer to develop. Samsung has shipped a 3D NAND device. Micron and SK Hynix... » read more

FinFET Based Designs: Power Analysis Considerations
By Aveek Sarkar - 10 Apr, 2014 - Comments: 2

Design teams working on mobile, computing, networking and other low power, high performance IPs and SoCs are migrating to FinFET-based technologies. However the benefits from their smaller sizes and the ability to deliver consistent performance at ultra-low sub-1V nominal supply voltage levels is outweighed by the worsening of power noise and reliability. As mentioned in an earlier blog on Powe... » read more

Looking Beyond Moore’s Law
By Mark LaPedus - 20 Feb, 2014 - Comments: 2

For decades, chip scaling has followed a simple linear curve. In this curve, the transistor gate-pitch scales at 0.7x every two years. This is the driving force behind Moore’s Law, which states that the number of transistors per chip roughly doubles every two years. But starting at the 16nm/14nm node, there is a change taking place in chip scaling. According to a chart from Imec, there are... » read more

What Goes Around Comes Around: Moore’s Law At 10nm And Beyond
By Greg Yeric - 13 Feb, 2014 - Comments: 2

Modified by Greg Yeric from original by Eric Fischer Gordon Moore penned his famous observation in an era when the people developing the process were also the people designing the circuits. Over time, things got more complicated and work specialization set in, but all was well in the world for many years as the fabs kept delivering on Moore’s Law. Yes, designers had to come up with lot... » read more

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