IBM, Intel And TSMC Roll Out finFETs

At IEDM, IBM, Intel and TSMC will present the latest details of their 16nm/14nm finFET technologies.


At the IEEE International Electron Devices Meeting (IEDM) in San Franciso, IBM, Intel and Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) this week will separately present the latest details of their respective 16nm/14nm finFET technologies.

As expected, Intel and TSMC will continue to use bulk CMOS. IBM will continue to go with rival silicon-on-insulator (SOI) technology. At IEDM, Intel will provide more details about its 14nm technology, while IBM and TSMC will offer fewer specifics about the technology.

Clearly, though, Intel is leading the finFET race in the market by a wide margin. At one time, the GlobalFoundries/Samsung duo appeared to be in second place, followed by TSMC, although TSMC appears to be closing the gap. Now, IBM is entering the finFET race, although Big Blue’s chip unit is being acquired by GlobalFoundries.

On Monday, meanwhile, Intel is expected to provide more details about its second-generation finFET process. The 14nm technology features a new sub-fin doping technique, self-aligned double patterning (SADP) and air-gapped interconnects. At 14nm, Intel used 193nm immersion lithography.

As expected, the 13-metal layer technology features a high-k/metal-gate stack and low-k dielectrics. Intel also went with taller and thinner fins. The technology also includes rectangular-shaped fins with an 8nm fin width and a 42nm fin height. Interconnect pitches are as low as 52nm.

In a paper, Intel described a 13-layer copper interconnect stack. Low-k dielectrics are used on eight layers. Two layers are based on air-gapped interconnect technology. “Air gaps are used at 80nm and 160nm minimum pitch layers and provide a 17% improvement in capacitance,” according to the paper from Intel. “A thick top metal is used for improved on-die power distribution.”

The process is also enabled by a fin profile optimization and a novel sub-fin doping technique. “Sub-fin doping of high performance transistors is achieved through solid-source doping to enable better optimization of punch-through stopper dopants,” according to the paper from Intel.

Intel improved the NMOS and PMOS performance at 14nm. “At 0.7V Vdd, 10nA/um Ioff, 42nm fin pitch and 70nm contacted gate pitch, saturated drive currents are 1.04mA/um (all drive currents are per-micron of layout width) for both NMOS and PMOS,” according to the paper. “Idsat is improved 15% for NMOS and 41% for PMOS over 22nm, and these are the best drive currents reported to-date for 14nm technology. NMOS and PMOS linear drive currents are 0.237mA/um and 0.203mA/um, respectively, at 10nA/um Ioff, Vgs=0.7V, and Vds=50mV.”

While Intel is ramping up the 14nm technology, TSMC recently accelerated its 16nm finFET production from the fourth quarter of 2015, to the second quarter of next year. TSMC has actually devised two 16nm finFET technologies. The second version, dubbed 16-FinFET plus, is re-optimized to provide an additional 15% speed boost and a 30% power reduction over the previous technology.

TSMC’s fin pitch is 48nm, but it did not disclose the fin height or width. “Poly-silicon deposition and gate patterning with a gate pitch of 90nm on the three-dimensional fin structure is followed by high-K metal gate RPG process,” according to a paper from TSMC. A M1/Mx metal pitch of 64nm is enabled by using 193nm immersion and multiple patterning.

SRAM speed has been improved by greater than 25%. “This improvement allows the use of a 512 bits per bit-line scheme instead of a 256 bits per bit-line scheme to reduce the periphery circuit size,” according to TSMC.

As expected, IBM took another approach by rolling out a 14nm finFET technology based on SOI. The architecture is integrated with an embedded DRAM, which enables an ultra-dense (0.0174um2) memory solution.

The fin pitch is 42nm and the interconnect is a 64nm pitch. IBM did not disclose the fin height or width. This technology provides up to 15 levels of copper layers and includes traditional low-k. It also features a high-k/metal-gate stack and an epi source/drain structure.

The technology has a >35% performance improvement over its 22nm planar technology. A broad range of Vts are enabled on chips through a dual workfunction process applied to both NFETs and PFETs.

This enables simultaneous optimization of both low Vt (high performance) and high Vt (low power) devices without reliance on problematic doping schemes. “This performance gain stretches over a broad Vt range (from 100nA/um HP FETs to sub 1nA/um LP and SRAM array FETs which are featured in many ASICs),” according to IBM.