tag: finFET

Dealing With Atoms
By Mark LaPedus - 13 Jul, 2015 - Comments: 0

Chipmakers are ramping up a new range of device architectures, such as 3D NAND and finFETs. But to enable current and future devices, IC vendors will require new breakthroughs, including tools that can process tiny structures and films, even at the atomic level. The problem? There are gaps in terms of techniques that can process chips at the atomic level. Looking to help fill part of the ... » read more

Case Studies In Double-Patterning Debug
By David Abercrombie - 18 Jun, 2015 - Comments: 0

Double patterning (DP) impacts just about every part of the design and manufacturing flows. However, the kinds of issues you encounter, the way they manifest themselves, and the ideal way to address them may be very different in different parts of these flows. I feel like I have spent a lot of time the last six months or so working with place and route (P&R) and chip finishing engineers on DP i... » read more

The Bumpy Road To 10nm FinFETs
By Mark LaPedus - 21 May, 2015 - Comments: 0

Foundry vendors are currently ramping up their 16nm/14nm [getkc id="185" kc_name="finFET"] processes in the market. Vendors are battling each other for business in the arena, although the migration from planar to finFETs is expected to be a slow and expensive process. Still, despite the challenges at 16nm/14nm, vendors are gearing up for the next battle in the foundry business—the 10nm nod... » read more

10nm Fab Watch
By Mark LaPedus - 21 May, 2015 - Comments: 1

When will the 10nm logic node happen? Analysts believe that foundry vendors will move into 10nm finFET volume production around 2017. Still others say the 10nm finFET ramp could take place anywhere from 2018 to 2020. The predictions are all over the map. One way to predict the timing, progress and demand for 10nm is simple: Follow the fabs. In fact, Intel, Samsung, TSMC and GlobalFound... » read more

One PHY Does Not Fit All
By Rita Horner - 14 May, 2015 - Comments: 0

Consumers expect their battery-operated mobile devices to be faster, smaller and more reliable while providing greater functionality at a reduced cost. Most of all, consumers demand longer battery life and 24/7 access to data. To meet these demands, consumer system-on-a-chip (SoC) designers must make tradeoffs between features, performance, power and cost. Enterprise SoC designers have their... » read more

Microarchitecture Design For Low Power
By Anand Iyer - 14 May, 2015 - Comments: 0

As designs move to finFET process nodes, dynamic power reduction has become a requirement. Designers have to eliminate or minimize all sources of redundant switching activity in order to reduce dynamic power in the design. In our last blog, we looked at dynamic power wastage due to redundant adders and multipliers and how to gate these operators to save power. We also mentioned a couple of m... » read more

Blog Review: April 22
By Jesse Allen - 22 Apr, 2015 - Comments: 0

DARPA thinks machine-brain interfaces are poised to become an industry-changing technology. Rambus' David G. Stork brings us emerging developments in the field from the Neural Engineering Boot Camp. If you live in an area that doesn't get quite enough sun for solar panels, how about a smart window that harvests energy from wind and rain? In this week's top five picks, Ansys' Justin Nescott a... » read more

Searching For 3D Metrology
By Mark LaPedus - 19 Mar, 2015 - Comments: 3

In the previous decade, chipmakers made a bold but necessary decision to select the [getkc id="185" kc_name="finFET"] as the next transistor architecture for the IC industry. Over time, though, chipmakers discovered that the finFET would present some challenges in the fab. Deposition, etch and lithography were the obvious hurdles, but chipmakers also saw a big gap in metrology. In fact,... » read more

Low Power Paradox
By Anand Iyer - 13 Mar, 2015 - Comments: 0

Power has been an important design challenge for quite some time. Leakage power started to grow in 90nm, and by 65nm it became a severe design issue. We have built many techniques to address leakage, most notably power gating. These techniques are complex and have an impact on the design as a whole. FinFET technologies are seen as a boon to this issue of leakage. There are references that qu... » read more

Manufacturing Bits: Feb. 24
By Mark LaPedus - 24 Feb, 2015 - Comments: 0

EUV progress report At the SPIE Advanced Lithography conference in San Jose, Calif., ASML Holding said that one customer, Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC), has exposed more than 1,000 wafers on an NXE:3300B EUV system in a single day. This is one step towards the insertion of EUV lithography in volume production. During a recent test run on the system, TSMC exposed 1,022 w... » read more

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