tag: finFETs

Bulk CMOS Vs. FD-SOI
By Mark LaPedus - 19 May, 2016 - Comments: 2

The leading edge of the chip market increasingly is divided over whether to move to finFETs or whether to stay at 28nm using different materials and potentially even advanced packaging. Decisions about which approach to take frequently boil down to performance, power, form factor, cost, and the maturity of the individual technologies. All of those can vary by market, by vendor and by process... » read more

The Evolving Thermal Landscape
By Ann Mutschler - 16 May, 2016 - Comments: 0

Managing heat in chips is becoming a precision balancing act at advanced nodes and with advanced packaging. While it's important to ensure that temperatures don't rise high enough to cause reliability problems, adding too much circuitry to control heat can reduce performance and lower energy efficiency. The most common approach to dealing with these issues is thermal simulation, which requir... » read more

Power-Centric Chip Architectures
By Ed Sperling - 12 May, 2016 - Comments: 0

As traditional scaling runs out of steam, new chip architectures are emerging with power as the starting point. While this trend has been unfolding for some time, it is getting an extra boost and sense of urgency as design teams weigh a growing number of design challenges and options across a variety of new markets. Among the options are [getkc id="196" kc_name="multi-patterning"] and [getkc... » read more

FinFET Scaling Reaches Thermal Limit
By Brian Bailey - 12 May, 2016 - Comments: 2

In 1974, Robert H. Dennard was working as an IBM researcher. He introduced the idea that MOSFETs would continue to work as voltage-controlled switches in conjunction with shrinking features, providing doping levels, the chip's geometry, and voltages are scaled along with those size reductions. This became known as Dennard's Law even though, just like Moore's Law, it was anything but a law. T... » read more

10nm Versus 7nm
By Mark LaPedus - 25 Apr, 2016 - Comments: 20

The silicon foundry business is heating up, as vendors continue to ramp their 16nm/14nm finFET processes. At the same time, they are racing each other to ship the next technologies on the roadmap—10nm and 7nm. But the landscape is complicated, with each vendor taking a different strategy. [getentity id="22865" e_name="Samsung"], for one, plans to ship its 10nm [getkc id="185" kc_name="fi... » read more

Foundries Expand Their Scope
By Ed Sperling - 21 Apr, 2016 - Comments: 0

By Ed Sperling & Mark LaPedus Major foundries are stepping up their offerings across a wide swath of technology nodes, specialty processes and advanced packaging—a recognition that end markets are fragmenting and that the path forward includes a mix of new and established processes. As the smart phone market flattens, there is no single "next big thing" to drive volume at the most ... » read more

Improving Transistor Reliability
By Katherine Derbyshire - 21 Apr, 2016 - Comments: 1

One of the more important challenges in reliability testing and simulation is the duty cycle dependence of degradation mechanisms such as negative bias temperature instability ([getkc id="278" kc_name="NBTI"]) and hot carrier injection (HCI). For example, as previously discussed, both the shift due to NBTI and the recovery of baseline behavior are very dependent on device workload. This is ... » read more

Calibre xACT Parasitic Extraction Supports Signal Integrity At Advanced Nodes
By Mentor, a Siemens Business - 21 Apr, 2016 - Comments: 0

At advanced nodes, signal integrity analysis requires precise characterization, which in turn requires an accurate extracted netlist. Models that handle new impacts on parasitic extraction at advanced nodes, including multi-patterning, finFETs, and resistance and capacitance effects, must be used. Learn how the Calibre xACT extraction tool supports these advanced foundry device models and leadi... » read more

Have Margins Outlived Their Usefulness?
By Aveek Sarkar - 20 Apr, 2016 - Comments: 0

To automate the process of solving complex design problems, the traditional approach has been to partition them into smaller, manageable tasks. For each task, we have built the best possible solution which we continuously refine over time. Additionally, we have managed the interdependencies between tasks by defining boundaries or margins; these often have been best- and worst-case values used t... » read more

Rightsizing Challenges Grow
By Ed Sperling - 20 Apr, 2016 - Comments: 0

Rightsizing chip architectures is getting much more complicated. There are more options to choose from, more potential bottlenecks, and many more choices about what process to use at what process node and for which markets and price points. Rightsizing is a way of targeting chips to specific application needs, supplying sufficient performance while minimizing power and cost. It has been a to... » read more

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