tag: finFETs

Pointing Fingers, Often In The Wrong Direction
By Ed Sperling - 08 May, 2014 - Comments: 0

Every design these days, regardless of whether it’s a processor, an SoC, an ASIC, FPGA or stacked die, relies on a combination of re-used and third-party intellectual property. No company—not even Intel, Apple or Samsung—has the capability of building everything itself within a highly compressed market window. There is a spectrum of IP use and re-use, of course. In some cases, it may i... » read more

FinFET-Based Designs: Power Sign-off Considerations
By Aveek Sarkar - 08 May, 2014 - Comments: 0

FinFET devices can operate at ultra-low sub-1V nominal supply voltage levels without impacting their delays. This allows for low power, higher performance designs needed for many of todays’ applications. These devices also have considerably higher drive strengths, allowing faster operating speeds. However, this can result in more localized di/dt current scenarios, and when coupled with more r... » read more

The Week In Review: Design
By Ed Sperling - 02 May, 2014 - Comments: 0

Tools CEVA integrated Bluetooth processing into its DSP cores. In addition to audio and video and always-on capabilities, the company is pitching the combination as an all-in-one, ultra-low-power solution for the wearable electronics market. So how big is this market opportunity? IDC predicts the wearable computing market will grow from 19.2 million units this year to 112 million units in 2... » read more

Blog Review: April 30
By Ed Sperling - 30 Apr, 2014 - Comments: 0

Applied Materials’ Jeremy Read points to a looming problem for the Internet of Things—legacy fabs that will require software upgrades and advanced process control. Also needed: Sensors attached to thousands of machines for predictive maintenance. Foundries are now ready for production finFETs. Cadence's Richard Goering captures the buzz at last week’s TSMC Tech Symposium, where the ro... » read more

Follow The Investments
By Ed Sperling - 24 Apr, 2014 - Comments: 0

Where is design heading over the next few years. The best way to tell that is to find out where the development dollars are going, and foundries and tools always precede actual designs. The foundries are starting to spend money—lots of it—on finFETs and 28nm. And while they’re talking about 2.5D and 3D, the money isn’t going there just yet. In fact, there are two different processes ... » read more

The Week In Review: Design
By Ed Sperling - 18 Apr, 2014 - Comments: 0

Certifications TSMC certified Mentor Graphics’ DFM, place and route and custom IC tools, as well as its SPICE simulator, for the 16nm finFET process.  The foundry also certified Cadence’s digital and custom/analog tools for that process, including physical verification, QRC extraction, timing sign off and its power integrity solution. And it certified Synopsys’ digital and custom soluti... » read more

Gaps In Metrology Could Impact Yield
By Mark LaPedus - 17 Apr, 2014 - Comments: 0

For some time, chipmakers have been developing new and complex chip architectures, such as 3D NAND, finFETs and stacked die. But manufacturing these types of chips is no simple task. It requires a robust fab flow to enable new IC designs with good yields. In fact, yield is becoming a more critical part of the flow. Yield is a broad term that means different things to different parts of the ... » read more

Searching For Rare Earths
By Mark LaPedus - 17 Apr, 2014 - Comments: 2

The semiconductor industry is pre-occupied with several and expensive technologies at once. One the device side, the industry is looking at new chip architectures, such as 3D NAND, finFETs and stacked die. On the manufacturing front, there is 450mm technology, next-generation lithography (NGL) and new materials. And that’s just the tip of the iceberg. Another technology that deserve... » read more

Favorite Forecast Fallacies
By Barry Pangrle - 14 Apr, 2014 - Comments: 0

It’s difficult to make predictions, especially about the future. – An Old Danish Proverb. The GSA Silicon Summit was held on Thursday, April 10th at the Computer History Museum in Mountain View, CA. The opening panel session was entitled Advancements in Nanoscale Processing. The panelists were Rob Aitken (ARM), Adam Brand (Applied Materials), Peter Huang (TSMC), Nick Kepler (VLSI Researc... » read more

Power Moves Up To First Place
By Ed Sperling - 10 Apr, 2014 - Comments: 2

Virtually every presentation delivered about semiconductor design or manufacturing these days—and every end product specification that uses advanced technology—incorporates some reference to power and/or energy. It has emerged as the most persistent, most problematic, and certainly the most talked about issue from conception to marketplace adoption. And the conversation only grows louder... » read more

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