tag: finFETs

Experts At The Table: Mobile Design Challenges
By Ed Sperling - 21 Oct, 2011 - Comments: 0

By Ed Sperling Low-Power Engineering sat down to discuss the increasing challenges of designing for mobile devices with Qi Wang, technical marketing group director at Cadence; Cary Chin, director of technical marketing for low-power solutions at Synopsys; Bernard Murphy, CTO of Atrenta; and Dave Reed, senior director of marketing at SpringSoft. What follows are excerpts of that conversation. ... » read more

Interconnect Power II
By Barry Pangrle - 08 Sep, 2011 - Comments: 0

Barry Pangrle After submitting last month’s blog, I read a very interesting article by Deepak Sekar analyzing Intel’s 22 nm FinFET technology versus a hypothetical planar 22nm CMOS technology. Beyond the advantages of being able to use a 140 mV reduction in the supply voltage for the trigate technology, Deepak did a breakdown analysis for the predicted power across a representative micropr... » read more

Extending Battery Life
By Ed Sperling - 21 Jul, 2011 - Comments: 0

By Ed Sperling In the past it was all about clock frequency. People bought the latest computer and frequently paid a premium because it could crunch numbers faster. But as computing moves from the desktop into handheld devices, that focus is radically changing. Low-Power Engineering caught up with Mark Bohr, senior fellow and director of Intel’s process architecture and integration, to ta... » read more

One On One: ARM CTO Mike Muller
By Ed Sperling - 01 Jul, 2011 - Comments: 0

LPE: How far does Moore’s Law extend forward and what are we likely to encounter along the way? Muller: The good news is there is no known solution for 7nm. That implies that between now and then it’s okay. When I talk to people they seem fairly confident they’re going to get there. Exactly how they don’t know. Will there be any miracles needed? Yes, probably one or two. But 14nm and ... » read more

5 Ways To Cut Power
By Ed Sperling - 16 Jun, 2011 - Comments: 0

By Ed Sperling Low energy consumption with minimal leakage has emerged as the most competitive element in an IC design, regardless of whether it involves a plug, a battery, or whether it’s powered by a gasoline engine. While components on an SoC aren’t always power-aware, they’ll have to be in the future as consumers focus first on energy efficiency. With rising fuel costs, a concern ... » read more

Tri-Gate’s Fallout
By Ed Sperling - 26 May, 2011 - Comments: 0

By David Lammers Intel Corp. dropped a rock into the pond of transistor technology when it announced its 22nm tri-gate technology in San Francisco earlier this month. The ripples continue to move out from that event, with impacts on IDMs, foundries, and fabless semiconductor companies being closely studied. Now that Intel has come out of the closet with its tri-gate technology, “the found... » read more

Planning For Physical Effects
By Ed Sperling - 06 May, 2011 - Comments: 0

The importance of Intel’s announcement that it has perfected 3D transistors and will roll them out this year should not be understated. This is a major breakthrough technologically, with major implications for power, performance and even competitiveness. FinFETs have been the subject of some intensive research for more than a decade, with the University of California at Berkeley leading the c... » read more

Material Effects: Trading Performance For Power
By Ed Sperling - 13 Jan, 2011 - Comments: 0

By Ann Steffora Mutschler Power impacts everything, even when it comes to semiconductor manufacturing materials. While bulk CMOS technology still reigns supreme, there are a number of advanced materials being suggested as replacements when it runs out of steam at around 15nm, including silicon on insulator (SOI)—particularly in combination with FinFET multigate structures on SOI—silicon ge... » read more

The Shape Of Things To Come
By Ed Sperling - 26 Aug, 2010 - Comments: 0

By David Lammers Tall or thin? That is the question facing semiconductor companies, now reaching an “intense” phase in development of the vertical finFET and planar ETSOI (extra thin silicon on insulator) transistors for the 22/20nm and 15/14nm technology generations. “This is a conservative industry,” said Raj Jammy, vice president of materials and emerging technologies at Sematech... » read more

Another Brick In The Wall
By Ed Sperling - 19 Feb, 2009 - Comments: 0

The wall is in sight.   Moore’s Law has propelled the semiconductor industry at an amazing velocity since it was first introduced in 1965, and despite some minor changes from 18 months to two years, we have pretty much stayed on course. In the past, most people thought we would hit the wall at 1 micron, and they thought it would happen again at 32nm. The road map appears pretty solid dow... » read more

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