tag: finFETs

Ivy Bridge Settles Old Bet
By Marc David Levenson - 16 Aug, 2012 - Comments: 0

Think back seven years to 2005. Those were boom times with the housing market rising, the dollar high, 65nm node chips on the horizon and EUV the great future lithography hope. EUVL was late for the next (45nm) node, but a great new idea had appeared to fill the gap—water immersion scanning with 193nm exposure! But how far could wet 193nm lithography go before EUVL or some new thing, such as ... » read more

What Comes After FinFETs?
By Ed Sperling - 16 Aug, 2012 - Comments: 0

By Mark LaPedus The semiconductor industry is currently making a major transition from conventional planar transistors to finFETs starting at 22nm. The question is what’s next? In the lab, IBM, Intel and others have demonstrated the ability to scale finFETs down to 5nm or so. If or when finFETs runs out of steam, there are no less than 18 different next-generation candidates that could o... » read more

Inflection Points
By Ed Sperling - 15 Aug, 2012 - Comments: 0

Semiconductor Manufacturing and Design talks with Paul Boudre, chief operating officer at Soitec, about FinFETs, industry inflection points, the end of life for planar transistors, bulk CMOS vs. SOI, the differences between fully depleted and partially depleted SOI, and the FD-SOI ecosystem. [youtube vid=8ZhfJLkImlk] » read more

More Design Rules Ahead
By Ed Sperling - 25 Jul, 2012 - Comments: 0

By Ed Sperling & Mark LaPedus For those companies that continue to push the limits of feature shrinkage, designs are about to become more difficult, far more expensive—and much more regulated. Two converging factors will force these changes. First, the limits of current 193nm immersion lithography mean companies now must double pattern at 20nm, and potentially quadruple pattern at 14n... » read more

Future Foundry Issues
By Ed Sperling - 13 Jul, 2012 - Comments: 0

Semiconductor Manufacturing & Design talks with Luigi Capodieci, fellow at GlobalFoundries, about EUV, the challenges at 20nm and beyond, and the future of the foundry model. [youtube vid=YXov4y0kpfU] » read more

Dealing With Variability
By Barry Pangrle - 12 Jul, 2012 - Comments: 0

By Barry Pangrle Process, voltage and temperature, a.k.a. PVT, are well known to designers who are working to complete “signoff” for their designs. In order for a design to be production-ready, it’s necessary to ensure that the design is going to yield parts at a sufficiently high percentage for profitability and that it will still operate within the expected variation of the process and... » read more

All Indicators Point North
By Ed Sperling - 28 Jun, 2012 - Comments: 0

Designing and producing chips has always been difficult, but the number of things that conspire to make it harder at 20nm is the longest in the history of the semiconductor industry. The list will grow longer still at 14nm and beyond, not to mention so expensive that one mistake will kill a company. While system engineers and architects look at the challenges on the front end, the problems ... » read more

Experts At The Table: Multipatterning
By Ed Sperling - 26 Jun, 2012 - Comments: 0

By Ed Sperling Semiconductor Manufacturing & Design sat down with Michael White, physical verification product line manager at Mentor Graphics; Luigi Capodieci, R&D fellow at GlobalFoundries; Lars Liebmann, IBM distinguished engineer; Rob Aitken, ARM fellow; Jean-Pierre Geronimi, CAD director at STMicroelectronics; and Kuang-Kuo Lin, director of foundry design enablement at Samsung Ele... » read more

Fabless-Foundry Model Under Stress
By Ed Sperling - 26 Jun, 2012 - Comments: 0

By Mark LaPedus The semiconductor roadmap was once a smooth and straightforward path, but chipmakers face a bumpy and challenging ride as they migrate to the 20nm node and beyond. Among the challenges seen on the horizon are the advent of 3D stacking, 450mm fabs, new transistor architectures, multi-patterning, and the questionable availability of extreme ultraviolet (EUV) lithography. ... » read more

FinFET Vs. Tri-Gate
By Barry Pangrle - 05 Apr, 2012 - Comments: 0

By Barry Pangrle A large portion of the Common Platform Technology Forum, recently held in Santa Clara, was dedicated to presentations about 14nm process technologies and FinFETS. If you missed the event and are interested, many of the presentations are available from a link off of the Common Platform home page. Dick James wrote a nice article about GlobalFoundries’ claim that its FinFETS ar... » read more

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